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mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2
[coreboot2.git] / src / soc / intel / cannonlake / vr_config.c
bloba01a455240c940348681ea164f26ee3f243b2bda
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_ids.h>
4 #include <device/pci_ops.h>
5 #include <fsp/api.h>
6 #include <soc/ramstage.h>
7 #include <soc/vr_config.h>
8 #include <console/console.h>
9 #include <intelblocks/cpulib.h>
10
11 static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
12 [VR_SYSTEM_AGENT] = {
13 .vr_config_enable = 1,
14 .psi1threshold = VR_CFG_AMP(20),
15 .psi2threshold = VR_CFG_AMP(5),
16 .psi3threshold = VR_CFG_AMP(1),
17 .psi3enable = 1,
18 .psi4enable = 1,
19 .imon_slope = 0,
20 .imon_offset = 0,
21 .icc_max = 0,
22 .voltage_limit = 1520,
23 },
24 [VR_IA_CORE] = {
25 .vr_config_enable = 1,
26 .psi1threshold = VR_CFG_AMP(20),
27 .psi2threshold = VR_CFG_AMP(5),
28 .psi3threshold = VR_CFG_AMP(1),
29 .psi3enable = 1,
30 .psi4enable = 1,
31 .imon_slope = 0,
32 .imon_offset = 0,
33 .icc_max = 0,
34 .voltage_limit = 1520,
35 },
36 [VR_GT_UNSLICED] = {
37 .vr_config_enable = 1,
38 .psi1threshold = VR_CFG_AMP(20),
39 .psi2threshold = VR_CFG_AMP(5),
40 .psi3threshold = VR_CFG_AMP(1),
41 .psi3enable = 1,
42 .psi4enable = 1,
43 .imon_slope = 0,
44 .imon_offset = 0,
45 .icc_max = 0,
46 .voltage_limit = 1520,
47 },
48 [VR_GT_SLICED] = {
49 .vr_config_enable = 1,
50 .psi1threshold = VR_CFG_AMP(20),
51 .psi2threshold = VR_CFG_AMP(5),
52 .psi3threshold = VR_CFG_AMP(1),
53 .psi3enable = 1,
54 .psi4enable = 1,
55 .imon_slope = 0,
56 .imon_offset = 0,
57 .icc_max = 0,
58 .voltage_limit = 1520,
59 },
60 };
61
62 struct vr_lookup_item {
63 uint16_t tdp_min;
64 enum chip_pl2_4_cfg pl2_4_cfg; /* Use 'value_not_set' for don't care */
65 uint16_t conf[NUM_VR_DOMAINS];
66 };
67
68 struct vr_lookup {
69 uint16_t mchid;
70 uint8_t num_items;
71 const struct vr_lookup_item *items;
72 };
73
74 #define VR_CONFIG(x, y) \
75 static const struct vr_lookup_item vr_config_##x##_##y[] =
76 #define VR_CONFIG_ICC(x) VR_CONFIG(x, ICC)
77 #define VR_CONFIG_LL(x) VR_CONFIG(x, LL)
78 #define VR_CONFIG_TDC(x) VR_CONFIG(x, TDC)
79
80 #define VR_REFITEM(x, y) { x, ARRAY_SIZE(vr_config_##x##_##y), vr_config_##x##_##y}
81 #define VR_REFITEM_ICC(x) VR_REFITEM(x, ICC)
82 #define VR_REFITEM_LL(x) VR_REFITEM(x, LL)
83 #define VR_REFITEM_TDC(x) VR_REFITEM(x, TDC)
84
85 static uint16_t load_table(const struct vr_lookup *tbl,
86 const int tbl_entries,
87 const int domain,
88 const uint16_t tdp,
89 const uint16_t mch_id)
90 {
91 const config_t *cfg = config_of_soc();
92
93 for (size_t i = 0; i < tbl_entries; i++) {
94 if (tbl[i].mchid != mch_id)
95 continue;
96
97 for (size_t j = 0; j < tbl[i].num_items; j++) {
98 if (tbl[i].items[j].tdp_min > tdp)
99 continue;
100
101 if ((tbl[i].items[j].pl2_4_cfg != value_not_set) &&
102 (tbl[i].items[j].pl2_4_cfg != cfg->cpu_pl2_4_cfg))
103 continue;
104
105 return tbl[i].items[j].conf[domain];
106 }
107 break;
108 }
109
110 printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__);
111
112 return 0;
113 }
114
115 /*
116 * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL.
117 * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL.
118 * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML.
119 *
120 * Platform Segment SA IA GT (GT/GTx)
121 * ---------------------------------------------------------------------
122 * CFL-U (28W) GT3 quad 8.5 64 64
123 * CFL-U (28W) GT3 dual 8.5 64 64
124 *
125 * CFL-H (45W) GT2 hex 11.1 128 0
126 * CFL-H (45W) GT2 quad 11.1 86 0
127 *
128 * CFL-S (95W) GT2 octa 11.1 193 45
129 *
130 * CFL-S (95W) GT2 hex 11.1 138 45
131 * CFL-S (65W) GT2 hex 11.1 133 45
132 * CFL-S (80W) GT2 hex 11.1 133 45
133 * CFL-S (35W) GT2 hex 11.1 104 35
134 *
135 * CFL-S (91W) GT2 quad 11.1 100 45
136 * CFL-S (83W) GT2 quad 11.1 100 45
137 * CFL-S (71W) GT2 quad 11.1 100 45
138 * CFL-S (65W) GT2 quad 11.1 79 45
139 * CFL-S (62W) GT2 quad 11.1 79 45
140 * CFL-S (35W) GT2 quad 11.1 66 35
141 *
142 * CFL-S (58W) GT2 dual 11.1 79 45
143 * CFL-S (54W) GT2 dual 11.1 58 45
144 * CFL-S (35W) GT2 dual 11.1 40 35
145 *
146 * CNL-U (15W) 13 34 0
147 *
148 * WHL-U (15W) GT2 quad 6 70 31
149 * WHL-U (15W) GT2 dual 6 35 31
150 *
151 * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31
152 * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31
153 * CML-U v1/v2 (15W) GT2 dual 6 35 31
154 *
155 * CML-H (65W) GT2 octa 11.1 192(165) 32
156 * CML-H (45W) GT2 octa 11.1 165(140) 32
157 * CML-H (45W) GT2 hex 11.1 140(128) 32
158 * CML-H (45W) GT2 quad 11.1 105(86) 32
159 *
160 * CML-S (125W)GT2 deca 11.1 245(210) 35
161 * CML-S (125W)GT2 octa 11.1 245(210) 35
162 * CML-S (125W)GT2 hex 11.1 140 35
163 * CML-S XeonW (80W) GT2 deca 11.1 210 35
164 * CML-S XeonW (80W) GT2 octa 11.1 210 35
165 * CML-S XeonW (80W) GT2 hex 11.1 140 35
166 * CML-S (65W) GT2 deca 11.1 210(175) 35
167 * CML-S (65W) GT2 octa 11.1 210(175) 35
168 * CML-S (65W) GT2 hex 11.1 140 35
169 * CML-S (35W) GT2 deca 11.1 140(104) 35
170 * CML-S (35W) GT2 octa 11.1 140(104) 35
171 * CML-S (35W) GT2 hex 11.1 104 35
172 * CML-S (65W) GT2 quad 11.1 102 35
173 * CML-S (35W) GT2 quad 11.1 65 35
174 * CML-S (58W) GT2 dual 11.1 60 35
175 * CML-S (35W) GT2 dual 11.1 55 35
176 *
177 * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0.
178 * The above values in () are for baseline.
179 */
180
181 VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_U) {
182 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
183 };
184 VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_Y) {
185 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
186 };
187 VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_4) {
188 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
189 };
190 VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_2) {
191 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
192 };
193 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U) {
194 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
195 };
196 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U_2) {
197 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
198 };
199 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_8) { /* undocumented */
200 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
201 };
202 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H) {
203 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
204 };
205 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_4) {
206 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 0, 0) },
207 };
208 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S) {
209 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
210 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
211 { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
212 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
213 };
214 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
215 { 58, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 35, 35) },
216 { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) },
217 { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) },
218 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) },
219 };
220 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_4) {
221 { 83, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
222 { 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
223 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
224 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
225 };
226 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_4) {
227 { 83, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
228 { 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
229 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
230 { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
231 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
232 };
233 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
234 { 91, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
235 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
236 { 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
237 { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
238 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
239 };
240 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
241 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
242 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
243 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
244 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
245 };
246 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_6) {
247 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
248 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
249 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
250 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
251 };
252 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_8) {
253 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
254 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
255 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
256 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
257 };
258 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
259 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
260 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
261 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
262 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
263 };
264 VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
265 { 127, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
266 { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
267 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
268 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
269 { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
270 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
271 };
272
273 VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT) {
274 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
275 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
276 };
277 VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_6_2) {
278 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
279 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
280 };
281 VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_2_2) {
282 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
283 };
284 VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_8_2) {
285 { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
286 { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32) },
287 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
288 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
289 };
290 VR_CONFIG_ICC(PCI_DID_INTEL_CML_H) {
291 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
292 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
293 };
294 VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_4_2) {
295 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32) },
296 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 32, 32) },
297 };
298 VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
299 {125, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
300 {125, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
301 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
302 { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
303 { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 175, 35, 35) },
304 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
305 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
306 };
307 VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
308 {125, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
309 {125, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
310 { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
311 { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
312 { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 175, 35, 35) },
313 { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
314 { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
315 };
316 VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
317 { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
318 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
319 };
320 VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_4) {
321 { 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 102, 35, 35) },
322 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35) },
323 };
324 VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_2) {
325 { 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 35, 35) },
326 { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35) },
327 };
328
329 static const struct vr_lookup vr_config_icc[] = {
330 VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_U),
331 VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_Y),
332 VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_4),
333 VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_2),
334 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U),
335 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U_2),
336 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_8),
337 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H),
338 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_4),
339 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2),
340 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4),
341 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8),
342 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_8),
343 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8),
344 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S),
345 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6),
346 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_4),
347 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_6),
348 VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_4),
349 VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT),
350 VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_6_2),
351 VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_2_2),
352 VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_8_2),
353 VR_REFITEM_ICC(PCI_DID_INTEL_CML_H),
354 VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_4_2),
355 VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2),
356 VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2),
357 VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
358 VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_4),
359 VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_2),
360 };
361
362 VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_U) {
363 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
364 };
365 VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_Y) {
366 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
367 };
368 VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_4) { /* unspecified */
369 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 0, 0) },
370 };
371 VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_2) { /* unspecified */
372 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 0, 0) },
373 };
374 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U) {
375 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
376 };
377 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U_2) {
378 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
379 };
380 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_8) {
381 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
382 };
383 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H) {
384 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
385 };
386 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_4) {
387 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
388 };
389 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_4) {
390 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
391 };
392 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_4) {
393 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
394 };
395 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_2) {
396 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
397 };
398 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_8) {
399 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
400 };
401 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_8) {
402 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
403 };
404 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_8) {
405 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
406 };
407 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S) {
408 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
409 };
410 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_6) {
411 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
412 };
413 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_6) {
414 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
415 };
416 VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_4) {
417 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
418 };
419 VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT) {
420 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
421 };
422 VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_6_2) {
423 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
424 };
425 VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_2_2) {
426 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1) },
427 };
428 VR_CONFIG_LL(PCI_DID_INTEL_CML_H_8_2) {
429 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
430 };
431 VR_CONFIG_LL(PCI_DID_INTEL_CML_H) {
432 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
433 };
434 VR_CONFIG_LL(PCI_DID_INTEL_CML_H_4_2) {
435 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
436 };
437 VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_8_2) {
438 { 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
439 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
440 };
441 VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_10_2) {
442 { 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
443 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
444 };
445 VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
446 {125, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
447 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
448 };
449 VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_4) {
450 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
451 };
452 VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_2) {
453 { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
454 };
455
456
457 static const struct vr_lookup vr_config_ll[] = {
458 VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_U),
459 VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_Y),
460 VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_4),
461 VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_2),
462 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U),
463 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U_2),
464 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_8),
465 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H),
466 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_4),
467 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_4),
468 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_4),
469 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_2),
470 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_8),
471 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_8),
472 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_8),
473 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S),
474 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_6),
475 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_6),
476 VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_4),
477 VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT),
478 VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_6_2),
479 VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_2_2),
480 VR_REFITEM_LL(PCI_DID_INTEL_CML_H_8_2),
481 VR_REFITEM_LL(PCI_DID_INTEL_CML_H),
482 VR_REFITEM_LL(PCI_DID_INTEL_CML_H_4_2),
483 VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_8_2),
484 VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_10_2),
485 VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
486 VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_4),
487 VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_2),
488 };
489
490 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_H) {
491 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
492 };
493 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S) {
494 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
495 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
496 { 35, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
497 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
498 };
499 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
500 { 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
501 { 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
502 { 35, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
503 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
504 };
505 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_4) {
506 { 83, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
507 { 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
508 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
509 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
510 };
511 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4) {
512 { 83, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
513 { 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
514 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
515 { 35, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
516 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
517 };
518 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
519 { 91, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
520 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
521 { 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
522 { 35, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
523 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
524 };
525 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
526 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
527 { 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
528 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
529 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
530 };
531 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_6) {
532 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
533 { 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
534 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
535 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
536 };
537 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_8) {
538 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
539 { 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
540 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
541 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
542 };
543 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
544 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
545 { 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
546 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
547 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
548 };
549 VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
550 { 127, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
551 { 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
552 { 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
553 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
554 { 35, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
555 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
556 };
557 VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT) {
558 { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
559 { 0, performance, VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
560 };
561 VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_6_2) {
562 { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
563 { 0, performance, VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
564 };
565 VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_2_2) {
566 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) },
567 };
568 VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_8_2) {
569 { 65, performance, VR_CFG_ALL_DOMAINS_TDC(10, 146, 25, 25) },
570 { 65, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 117, 25, 25) },
571 { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25) },
572 { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 86, 25, 25) },
573 };
574 VR_CONFIG_TDC(PCI_DID_INTEL_CML_H) {
575 { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25) },
576 { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
577 };
578 VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_4_2) {
579 { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
580 { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 60, 25, 25) },
581 };
582 VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
583 { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
584 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
585 };
586 VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
587 { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
588 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
589 };
590 VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
591 {125, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 132, 28, 28) },
592 { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 104, 28, 28) },
593 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28) },
594 };
595 VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_4) {
596 { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 68, 28, 28) },
597 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 42, 28, 28) },
598 };
599 VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_2) {
600 { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 38, 28, 28) },
601 { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 25, 28, 28) },
602 };
603
604 static const struct vr_lookup vr_config_tdc[] = {
605 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_H),
606 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S),
607 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2),
608 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_4),
609 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4),
610 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4),
611 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6),
612 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_6),
613 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_8),
614 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8),
615 VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8),
616 VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT),
617 VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_6_2),
618 VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_2_2),
619 VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_8_2),
620 VR_REFITEM_TDC(PCI_DID_INTEL_CML_H),
621 VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_4_2),
622 VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2),
623 VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2),
624 VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
625 VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_4),
626 VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_2),
627 };
628
629 static uint16_t get_sku_voltagelimit(int domain)
630 {
631 return 1520;
632 }
633
634 static uint16_t get_sku_icc_max(const int domain,
635 const uint16_t tdp,
636 const uint16_t mch_id,
637 const uint16_t igd_id)
638 {
639 if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED)))
640 return 0;
641
642 return load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), domain, tdp, mch_id);
643 }
644
645 void fill_vr_domain_config(void *params,
646 int domain, const struct vr_config *chip_cfg)
647 {
648 FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params;
649 const struct vr_config *cfg;
650 static uint16_t mch_id = 0, igd_id = 0;
651 const uint16_t tdp = cpu_get_power_max() / 1000;
652
653 if (!mch_id) {
654 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
655 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
656 }
657 if (!igd_id) {
658 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
659 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
660 }
661
662 if (domain < 0 || domain >= NUM_VR_DOMAINS)
663 return;
664
665 /* Use device tree override if requested. */
666 if (chip_cfg->vr_config_enable)
667 cfg = chip_cfg;
668 else
669 cfg = &default_configs[domain];
670
671 vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
672 vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
673 vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
674 vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
675 vr_params->Psi3Enable[domain] = cfg->psi3enable;
676 vr_params->Psi4Enable[domain] = cfg->psi4enable;
677 vr_params->ImonSlope[domain] = cfg->imon_slope;
678 vr_params->ImonOffset[domain] = cfg->imon_offset;
679 printk(BIOS_INFO, "VR config[%d]:\n", domain);
680 printk(BIOS_INFO, " Psi1Threshold: %u\n", cfg->psi1threshold);
681 printk(BIOS_INFO, " Psi2Threshold: %u\n", cfg->psi2threshold);
682 printk(BIOS_INFO, " Psi3Threshold: %u\n", cfg->psi3threshold);
683 printk(BIOS_INFO, " Psi3Enable: %u\n", cfg->psi3enable);
684 printk(BIOS_INFO, " Psi4Enable: %u\n", cfg->psi4enable);
685 printk(BIOS_INFO, " ImonSlope: %u\n", cfg->imon_slope);
686 printk(BIOS_INFO, " ImonOffset: %u\n", cfg->imon_offset);
687
688 /* If board provided non-zero value, use it. */
689 if (cfg->voltage_limit)
690 vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
691 else
692 vr_params->VrVoltageLimit[domain] = get_sku_voltagelimit(domain);
693 printk(BIOS_INFO, " VrVoltageLimit: %u\n", vr_params->VrVoltageLimit[domain]);
694
695 if (cfg->icc_max)
696 vr_params->IccMax[domain] = cfg->icc_max;
697 else
698 vr_params->IccMax[domain] = get_sku_icc_max(domain, tdp, mch_id, igd_id);
699 printk(BIOS_INFO, " IccMax: %u\n", vr_params->IccMax[domain]);
700
701 if (cfg->ac_loadline)
702 vr_params->AcLoadline[domain] = cfg->ac_loadline;
703 else
704 vr_params->AcLoadline[domain] = load_table(vr_config_ll,
705 ARRAY_SIZE(vr_config_ll),
706 domain, tdp, mch_id);
707 printk(BIOS_INFO, " AcLoadline: %u\n", vr_params->AcLoadline[domain]);
708
709 if (cfg->dc_loadline)
710 vr_params->DcLoadline[domain] = cfg->dc_loadline;
711 else
712 vr_params->DcLoadline[domain] = load_table(vr_config_ll,
713 ARRAY_SIZE(vr_config_ll),
714 domain, tdp, mch_id);
715 printk(BIOS_INFO, " DcLoadline: %u\n", vr_params->DcLoadline[domain]);
716
717 vr_params->TdcEnable[domain] = !cfg->tdc_disable;
718 printk(BIOS_INFO, " TdcEnable: %u\n", vr_params->TdcEnable[domain]);
719
720 if (cfg->tdc_powerlimit)
721 vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit;
722 else
723 vr_params->TdcPowerLimit[domain] = load_table(vr_config_tdc,
724 ARRAY_SIZE(vr_config_tdc),
725 domain, tdp, mch_id);
726 printk(BIOS_INFO, " TdcPowerLimit: %u\n", vr_params->TdcPowerLimit[domain]);
727 }
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