src/soc/intel/xeon_sp/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen.h>
   4 #include <acpi/acpigen_pci.h>
   5 #include <assert.h>
   6 #include <device/pci_ops.h>
   7 #include <intelblocks/acpi.h>
   8 #include <soc/chip_common.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/util.h>
  11 #include <stdint.h>
  12 #include <stdio.h>
  13 #include <stdlib.h>
  14
  15 #include "chip.h"
  16
  17 /*
  18  * List of supported C-states in this processor.
  19  */
  20 enum {
  21         C_STATE_C1,     /* 0 */
  22         C_STATE_C3,     /* 1 */
  23         C_STATE_C6,     /* 2 */
  24         C_STATE_C7,     /* 3 */
  25         NUM_C_STATES
  26 };
  27
  28 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  29         [C_STATE_C1] = {
  30                 /* C1 */
  31                 .latency = 1,
  32                 .power = 0x3e8,
  33                 .resource = MWAIT_RES(0, 0),
  34         },
  35         [C_STATE_C3] = {
  36                 /* C3 */
  37                 .latency = 15,
  38                 .power = 0x1f4,
  39                 .resource = MWAIT_RES(1, 0),
  40         },
  41         [C_STATE_C6] = {
  42                 /* C6 */
  43                 .latency = 41,
  44                 .power = 0x15e,
  45                 .resource = MWAIT_RES(2, 0),
  46         },
  47         [C_STATE_C7] = {
  48                 /* C7 */
  49                 .latency = 41,
  50                 .power = 0x0c8,
  51                 .resource = MWAIT_RES(3, 0),
  52         }
  53 };
  54
  55 /* Max states supported */
  56 static int cstate_set_all[] = {
  57         C_STATE_C1,
  58         C_STATE_C3,
  59         C_STATE_C6,
  60         C_STATE_C7
  61 };
  62
  63 static int cstate_set_c1_c6[] = {
  64         C_STATE_C1,
  65         C_STATE_C6,
  66 };
  67
  68 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  69 {
  70         static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
  71         int *cstate_set;
  72         int i;
  73
  74         const config_t *config = config_of_soc();
  75
  76         const enum acpi_cstate_mode states = config->cstate_states;
  77
  78         switch (states) {
  79         case CSTATES_C1C6:
  80                 *entries = ARRAY_SIZE(cstate_set_c1_c6);
  81                 cstate_set = cstate_set_c1_c6;
  82                 break;
  83         case CSTATES_ALL:
  84         default:
  85                 *entries = ARRAY_SIZE(cstate_set_all);
  86                 cstate_set = cstate_set_all;
  87                 break;
  88         }
  89
  90         for (i = 0; i < *entries; i++) {
  91                 map[i] = cstate_map[cstate_set[i]];
  92                 map[i].ctype = i + 1;
  93         }
  94         return map;
  95 }
  96
  97 void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
  98 {
  99         const union xeon_domain_path dn = {
 100                 .domain_path = dev_get_domain_id(dev)
 101         };
 102
 103         assert(dn.socket < CONFIG_MAX_SOCKET);
 104         assert(dn.stack < 16);
 105         assert(prefix != NULL && strlen(prefix) == 2);
 106
 107         if (dn.socket >= CONFIG_MAX_SOCKET || dn.stack >= 16 ||
 108             !prefix || strlen(prefix) != 2)
 109                 return;
 110
 111         char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
 112         snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack);
 113         dev->name = name;
 114 }
 115
 116 const char *soc_acpi_name(const struct device *dev)
 117 {
 118         if (dev->path.type == DEVICE_PATH_DOMAIN)
 119                 return dev->name;
 120
 121         /* FIXME: Add SoC specific device names here */
 122
 123         return NULL;
 124 }
 125
 126 void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain,
 127                                 const uint32_t granted_pcie_features,
 128                                 const bool is_cxl_domain,
 129                                 const uint32_t granted_cxl_features)
 130 {
 131         acpigen_write_method("_OSC", 4);
 132
 133         acpigen_write_return_namestr("\\_SB.POSC");
 134         acpigen_emit_byte(ARG0_OP);
 135         acpigen_emit_byte(ARG1_OP);
 136         acpigen_emit_byte(ARG2_OP);
 137         acpigen_emit_byte(ARG3_OP);
 138         acpigen_write_integer(granted_pcie_features);
 139         acpigen_write_integer(is_cxl_domain);
 140         acpigen_write_integer(granted_cxl_features);
 141
 142         acpigen_pop_len();
 143 }
 144
 145 static bool read_physical_slot_number(const struct device *dev, uint8_t *psn)
 146 {
 147         if (!is_pci(dev))
 148                 return false;
 149
 150         const size_t pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 151         if (!pos)
 152                 return false;
 153
 154         u32 sltcap = pci_read_config32(dev, pos + PCI_EXP_SLTCAP);
 155         *psn = ((sltcap >> 19) & 0x1FF);
 156         return true;
 157 }
 158
 159 static void acpigen_write_pci_root_port_devices(const struct device *rp)
 160 {
 161         uint8_t psn;
 162         bool have_psn = read_physical_slot_number(rp, &psn);
 163
 164         struct device *dev = NULL;
 165         while ((dev = dev_bus_each_child(rp->downstream, dev))) {
 166                 if (!is_pci(dev))
 167                         continue;
 168                 const char *name = acpi_device_name(dev);
 169                 if (!name)
 170                         continue;
 171                 acpigen_write_device(name);
 172                 acpigen_write_ADR_pci_device(dev);
 173                 if (have_psn)
 174                         acpigen_write_name_integer("_SUN", psn);
 175                 acpigen_pop_len();
 176         }
 177 }
 178
 179 void acpigen_write_pci_root_port(const struct device *rp)
 180 {
 181         const char *acpi_scope = acpi_device_scope(rp);
 182         if (!acpi_scope)
 183                 return;
 184         acpigen_write_scope(acpi_scope);
 185
 186         const char *acpi_name = acpi_device_name(rp);
 187         if (!acpi_name)
 188                 return;
 189         acpigen_write_device(acpi_name);
 190         acpigen_write_ADR_pci_device(rp);
 191         acpigen_write_pci_root_port_devices(rp);
 192
 193         acpigen_pop_len();
 194         acpigen_pop_len();
 195 }