src/soc/intel/xeon_sp/cpx/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <acpi/acpigen_pci.h>
   3 #include <arch/ioapic.h>
   4 #include <console/console.h>
   5 #include <console/debug.h>
   6 #include <cpu/x86/mp.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <gpio.h>
  10 #include <intelblocks/acpi.h>
  11 #include <intelblocks/lpc_lib.h>
  12 #include <intelblocks/p2sb.h>
  13 #include <soc/acpi.h>
  14 #include <soc/chip_common.h>
  15 #include <soc/numa.h>
  16 #include <soc/pch.h>
  17 #include <soc/soc_pch.h>
  18 #include <soc/ramstage.h>
  19 #include <soc/p2sb.h>
  20 #include <soc/soc_util.h>
  21 #include <soc/util.h>
  22 #include <soc/pci_devs.h>
  23
  24 /* UPD parameters to be initialized before SiliconInit */
  25 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
  26 {
  27         mainboard_silicon_init_params(silupd);
  28 }
  29
  30 static struct device_operations cpu_bus_ops = {
  31         .read_resources = noop_read_resources,
  32         .set_resources = noop_set_resources,
  33         .init = mp_cpu_bus_init,
  34         .acpi_fill_ssdt = generate_cpu_entries,
  35 };
  36
  37 struct pci_operations soc_pci_ops = {
  38         .set_subsystem = pci_dev_set_subsystem,
  39 };
  40
  41 static void chip_enable_dev(struct device *dev)
  42 {
  43         /* Set the operations if it is a special bus type */
  44         if (dev->path.type == DEVICE_PATH_DOMAIN) {
  45                 /* domain ops are assigned at their creation */
  46         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
  47                 dev->ops = &cpu_bus_ops;
  48         } else if (dev->path.type == DEVICE_PATH_GPIO) {
  49                 block_gpio_enable(dev);
  50         }
  51 }
  52
  53 static void iio_write_mask(u16 bus, u16 dev, u8 func)
  54 {
  55         pci_devfn_t device = PCI_DEV(bus, dev, func);
  56         u32 val = pci_s_read_config32(device, IIO_XPUNCCERRMSK_REG);
  57         val |= (SENT_PCIE_UNSUPP_MASK | RCVD_PCIE_CA_STS_MASK | RCVD_PCIE_UR_STS_MASK);
  58         pci_s_write_config32(device, IIO_XPUNCCERRMSK_REG, val);
  59
  60         val = pci_s_read_config32(device, RP_UNCERRMSK);
  61         val |= (SURPRISE_DWN_ERR_MSK | UNSUPPORTED_REQ_ERR_MSK);
  62         pci_s_write_config32(device, RP_UNCERRMSK, val);
  63 }
  64
  65 static void iio_dmi_en_masks(void)
  66 {
  67         pci_devfn_t device;
  68         u32 val;
  69         device = PCI_DEV(DMI_BUS_INDEX, DMI_DEV, DMI_FUNC);
  70         val = pci_s_read_config32(device, IIO_XPUNCCERRMSK_REG);
  71         val |= (SENT_PCIE_UNSUPP_MASK | RCVD_PCIE_CA_STS_MASK | RCVD_PCIE_UR_STS_MASK);
  72         pci_s_write_config32(device, IIO_XPUNCCERRMSK_REG, val);
  73
  74         val = pci_s_read_config32(device, DMI_UNCERRMSK);
  75         val |= (ECRC_ERR | MLFRMD_TLP | RCV_BUF_OVRFLOW | FLOW_CNTR | POISON_TLP | DLL_PRT_ERR);
  76         pci_s_write_config32(device, DMI_UNCERRMSK, val);
  77 }
  78
  79 static void iio_enable_masks(void)
  80 {
  81         struct iiostack_resource iio = {0};
  82         get_iiostack_info(&iio);
  83         int i, k;
  84         for (i = 0; i < iio.no_of_stacks; i++) {
  85                 const STACK_RES *st = &iio.res[i];
  86                 if (st->BusBase > 0 && st->BusBase != 0xff) {
  87                         for (k = 0; k < DEVICES_PER_IIO_STACK; k++) {
  88                                 printk(BIOS_DEBUG, "%s: bus:%x dev:%x func:%x\n", __func__,
  89                                         st->BusBase, k, 0);
  90                                 iio_write_mask(st->BusBase, k, 0);
  91                         }
  92                 }
  93         }
  94         iio_dmi_en_masks();
  95 }
  96
  97 static void set_pcu_locks(void)
  98 {
  99         struct device *dev = NULL;
 100
 101         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
 102                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
 103                 pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
 104                 pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
 105                                 PKG_PWR_LIM_LOCK_UPR);
 106                 pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO,
 107                                 TURBO_ACTIVATION_RATIO_LOCK);
 108         }
 109
 110         dev = NULL;
 111         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
 112                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
 113                 pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK);
 114         }
 115
 116         dev = NULL;
 117         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
 118                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
 119                 pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT,
 120                                 PP_PWR_LIM_LOCK);
 121                 pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR,
 122                                 DRAM_POWER_INFO_LOCK_UPR);
 123         }
 124
 125         dev = NULL;
 126         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) {
 127                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
 128                 pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
 129                 pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK);
 130         }
 131 }
 132
 133 static void set_imc_locks(void)
 134 {
 135         struct device *dev = 0;
 136         while ((dev = dev_find_device(PCI_VID_INTEL, IMC_M2MEM_DEVID, dev)))
 137                 pci_or_config32(dev, IMC_M2MEM_TIMEOUT, TIMEOUT_LOCK);
 138 }
 139
 140 static void set_upi_locks(void)
 141 {
 142         struct device *dev = 0;
 143         while ((dev = dev_find_device(PCI_VID_INTEL, UPI_LL_CR_DEVID, dev)))
 144                 pci_or_config32(dev, UPI_LL_CR_KTIMISCMODLCK, KTIMISCMODLCK_LOCK);
 145 }
 146
 147 static void chip_final(void *data)
 148 {
 149         /* Lock SBI */
 150         pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK);
 151
 152         /* LOCK PAM */
 153         pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);
 154
 155         set_pcu_locks();
 156         set_imc_locks();
 157         set_upi_locks();
 158
 159         p2sb_hide();
 160         iio_enable_masks();
 161         set_bios_init_completion();
 162 }
 163
 164 static void chip_init(void *data)
 165 {
 166         unlock_pam_regions();
 167
 168         printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
 169         fsp_silicon_init();
 170
 171         setup_pds();
 172         attach_iio_stacks();
 173
 174         override_hpet_ioapic_bdf();
 175         pch_enable_ioapic();
 176         pch_lock_dmictl();
 177         p2sb_unhide();
 178 }
 179
 180 struct chip_operations soc_intel_xeon_sp_cpx_ops = {
 181         .name = "Intel Cooper Lake-SP",
 182         .enable_dev = chip_enable_dev,
 183         .init = chip_init,
 184         .final = chip_final,
 185 };