src/soc/intel/xeon_sp/cpx/soc_acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpigen.h>
   4 #include <arch/smp/mpspec.h>
   5 #include <arch/vga.h>
   6 #include <assert.h>
   7 #include <cpu/intel/turbo.h>
   8 #include <device/mmio.h>
   9 #include <device/pci.h>
  10 #include <intelblocks/acpi.h>
  11 #include <intelblocks/cpulib.h>
  12 #include <soc/acpi.h>
  13 #include <soc/iomap.h>
  14 #include <soc/msr.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/pm.h>
  17 #include <soc/soc_util.h>
  18 #include <soc/util.h>
  19
  20 int soc_madt_sci_irq_polarity(int sci)
  21 {
  22         if (sci >= 20)
  23                 return MP_IRQ_POLARITY_LOW;
  24         else
  25                 return MP_IRQ_POLARITY_HIGH;
  26 }
  27
  28 uint32_t soc_read_sci_irq_select(void)
  29 {
  30         struct device *dev = PCH_DEV_PMC;
  31
  32         if (!dev)
  33                 return 0;
  34
  35         return pci_read_config32(dev, PMC_ACPI_CNT);
  36 }
  37
  38 void soc_fill_fadt(acpi_fadt_t *fadt)
  39 {
  40         /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
  41         fadt->flags &=  ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE);
  42 }
  43
  44 /* TODO: See if we can use the common generate_p_state_entries */
  45 void soc_power_states_generation(int core, int cores_per_package)
  46 {
  47         int ratio_min, ratio_max, ratio_turbo, ratio_step;
  48         int coord_type, power_max, power_unit, num_entries;
  49         int ratio, power, clock, clock_max;
  50         msr_t msr;
  51
  52         /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
  53         msr = rdmsr(MSR_MISC_PWR_MGMT);
  54         if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
  55                 coord_type = SW_ANY;
  56         else
  57                 coord_type = HW_ALL;
  58
  59         /* Get bus ratio limits and calculate clock speeds */
  60         msr = rdmsr(MSR_PLATFORM_INFO);
  61         ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
  62
  63         /* Determine if this CPU has configurable TDP */
  64         if (cpu_config_tdp_levels()) {
  65                 /* Set max ratio to nominal TDP ratio */
  66                 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
  67                 ratio_max = msr.lo & 0xff;
  68         } else {
  69                 /* Max Non-Turbo Ratio */
  70                 ratio_max = (msr.lo >> 8) & 0xff;
  71         }
  72         clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
  73
  74         /* Calculate CPU TDP in mW */
  75         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
  76         power_unit = 2 << ((msr.lo & 0xf) - 1);
  77         msr = rdmsr(MSR_PKG_POWER_SKU);
  78         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
  79
  80         /* Write _PCT indicating use of FFixedHW */
  81         acpigen_write_empty_PCT();
  82
  83         /* Write _PPC with no limit on supported P-state */
  84         acpigen_write_PPC_NVS();
  85
  86         /* Write PSD indicating configured coordination type */
  87         acpigen_write_PSD_package(core, 1, coord_type);
  88
  89         /* Add P-state entries in _PSS table */
  90         acpigen_write_name("_PSS");
  91
  92         /* Determine ratio points */
  93         ratio_step = PSS_RATIO_STEP;
  94         num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
  95         if (num_entries > PSS_MAX_ENTRIES) {
  96                 ratio_step += 1;
  97                 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
  98         }
  99
 100         /* P[T] is Turbo state if enabled */
 101         if (get_turbo_state() == TURBO_ENABLED) {
 102                 /* _PSS package count including Turbo */
 103                 acpigen_write_package(num_entries + 2);
 104
 105                 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 106                 ratio_turbo = msr.lo & 0xff;
 107
 108                 /* Add entry for Turbo ratio */
 109                 acpigen_write_PSS_package(
 110                         clock_max + 1,          /* MHz */
 111                         power_max,              /* mW */
 112                         PSS_LATENCY_TRANSITION, /* lat1 */
 113                         PSS_LATENCY_BUSMASTER,  /* lat2 */
 114                         ratio_turbo << 8,       /* control */
 115                         ratio_turbo << 8);      /* status */
 116         } else {
 117                 /* _PSS package count without Turbo */
 118                 acpigen_write_package(num_entries + 1);
 119         }
 120
 121         /* First regular entry is max non-turbo ratio */
 122         acpigen_write_PSS_package(
 123                 clock_max,              /* MHz */
 124                 power_max,              /* mW */
 125                 PSS_LATENCY_TRANSITION, /* lat1 */
 126                 PSS_LATENCY_BUSMASTER,  /* lat2 */
 127                 ratio_max << 8,         /* control */
 128                 ratio_max << 8);        /* status */
 129
 130         /* Generate the remaining entries */
 131         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 132              ratio >= ratio_min; ratio -= ratio_step) {
 133                 /* Calculate power at this ratio */
 134                 power = common_calculate_power_ratio(power_max, ratio_max, ratio);
 135                 clock = ratio * CONFIG_CPU_BCLK_MHZ;
 136                 //clock = 1;
 137                 acpigen_write_PSS_package(
 138                         clock,                  /* MHz */
 139                         power,                  /* mW */
 140                         PSS_LATENCY_TRANSITION, /* lat1 */
 141                         PSS_LATENCY_BUSMASTER,  /* lat2 */
 142                         ratio << 8,             /* control */
 143                         ratio << 8);            /* status */
 144         }
 145
 146         /* Fix package length */
 147         acpigen_pop_len();
 148 }