1 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
9 * Reset mapping for Lewisburg PCH. See page 428, Intel Doc #336067-007US
11 * 01 = Host Deep Reset
15 static const struct reset_mapping rst_map
[] = {
16 { .logical
= PAD_CFG0_LOGICAL_RESET_RSMRST
, .chipset
= 0U << 30 },
17 { .logical
= PAD_CFG0_LOGICAL_RESET_DEEP
, .chipset
= 1U << 30 },
18 { .logical
= PAD_CFG0_LOGICAL_RESET_PLTRST
, .chipset
= 2U << 30 },
21 static const struct pad_group lewisburg_community0_groups
[] = {
22 INTEL_GPP(GPP_A0
, GPP_A0
, GPP_A23
), /* GPP A */
23 INTEL_GPP(GPP_A0
, GPP_B0
, GPP_B23
), /* GPP B */
24 INTEL_GPP(GPP_A0
, GPP_F0
, GPP_F23
), /* GPP F */
27 static const struct pad_group lewisburg_community1_groups
[] = {
28 INTEL_GPP(GPP_C0
, GPP_C0
, GPP_C23
), /* GPP C */
29 INTEL_GPP(GPP_C0
, GPP_D0
, GPP_D23
), /* GPP D */
30 INTEL_GPP(GPP_C0
, GPP_E0
, GPP_E12
), /* GPP E */
33 static const struct pad_group lewisburg_community3_groups
[] = {
34 INTEL_GPP(GPP_I0
, GPP_I0
, GPP_I10
), /* GPP I */
37 static const struct pad_group lewisburg_community4_groups
[] = {
38 INTEL_GPP(GPP_J0
, GPP_J0
, GPP_J23
), /* GPP F */
39 INTEL_GPP(GPP_J0
, GPP_K0
, GPP_K10
), /* GPP K */
42 static const struct pad_group lewisburg_community5_groups
[] = {
43 INTEL_GPP(GPP_G0
, GPP_G0
, GPP_G23
), /* GPP G */
44 INTEL_GPP(GPP_G0
, GPP_H0
, GPP_H23
), /* GPP H */
45 INTEL_GPP(GPP_G0
, GPP_L0
, GPP_L19
), /* GPP L */
48 static const struct pad_group lewisburg_community2_groups
[] = {
49 INTEL_GPP(GPD0
, GPD0
, GPD11
), /* GPP GDP */
52 static const struct pad_community lewisburg_gpio_communities
[] = {
53 [COMM_0
] = { /* GPIO Community 0: GPP A, B, F */
57 .num_gpi_regs
= NUM_GPIO_COM0_GPI_REGS
,
58 .pad_cfg_base
= PAD_CFG_BASE
,
59 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
60 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
61 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
62 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
63 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
64 .gpi_nmi_sts_reg_0
= GPI_NMI_STS_0
,
65 .gpi_nmi_en_reg_0
= GPI_NMI_EN_0
,
66 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
68 .acpi_path
= "\\_SB.PCI0.GPIO",
70 .num_reset_vals
= ARRAY_SIZE(rst_map
),
71 .groups
= lewisburg_community0_groups
,
72 .num_groups
= ARRAY_SIZE(lewisburg_community0_groups
),
74 [COMM_1
] = { /* GPIO Community 1: GPP C, D, E */
78 .num_gpi_regs
= NUM_GPIO_COM1_GPI_REGS
,
79 .pad_cfg_base
= PAD_CFG_BASE
,
80 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
81 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
82 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
83 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
84 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
85 .gpi_nmi_sts_reg_0
= GPI_NMI_STS_0
,
86 .gpi_nmi_en_reg_0
= GPI_NMI_EN_0
,
87 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
89 .acpi_path
= "\\_SB.PCI0.GPIO",
91 .num_reset_vals
= ARRAY_SIZE(rst_map
),
92 .groups
= lewisburg_community1_groups
,
93 .num_groups
= ARRAY_SIZE(lewisburg_community1_groups
),
95 [COMM_3
] = { /* GPIO Community 3: GPP I */
99 .num_gpi_regs
= NUM_GPIO_COM3_GPI_REGS
,
100 .pad_cfg_base
= PAD_CFG_BASE
,
101 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
102 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
103 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
104 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
105 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
106 .gpi_nmi_sts_reg_0
= GPI_NMI_STS_0
,
107 .gpi_nmi_en_reg_0
= GPI_NMI_EN_0
,
108 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
110 .acpi_path
= "\\_SB.PCI0.GPIO",
111 .reset_map
= rst_map
,
112 .num_reset_vals
= ARRAY_SIZE(rst_map
),
113 .groups
= lewisburg_community3_groups
,
114 .num_groups
= ARRAY_SIZE(lewisburg_community3_groups
),
116 [COMM_4
] = { /* GPIO Community 4: GPP F, G */
117 .port
= PID_GPIOCOM4
,
120 .num_gpi_regs
= NUM_GPIO_COM4_GPI_REGS
,
121 .pad_cfg_base
= PAD_CFG_BASE
,
122 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
123 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
124 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
125 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
126 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
127 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
129 .acpi_path
= "\\_SB.PCI0.GPIO",
130 .reset_map
= rst_map
,
131 .num_reset_vals
= ARRAY_SIZE(rst_map
),
132 .groups
= lewisburg_community4_groups
,
133 .num_groups
= ARRAY_SIZE(lewisburg_community4_groups
),
135 [COMM_5
] = { /* GPIO Community 5: GPP G, H, L */
136 .port
= PID_GPIOCOM5
,
139 .num_gpi_regs
= NUM_GPIO_COM5_GPI_REGS
,
140 .pad_cfg_base
= PAD_CFG_BASE
,
141 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
142 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
143 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
144 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
145 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
146 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
148 .acpi_path
= "\\_SB.PCI0.GPIO",
149 .reset_map
= rst_map
,
150 .num_reset_vals
= ARRAY_SIZE(rst_map
),
151 .groups
= lewisburg_community5_groups
,
152 .num_groups
= ARRAY_SIZE(lewisburg_community5_groups
),
154 [COMM_2
] = { /* GPIO Community 2: GPD */
155 .port
= PID_GPIOCOM2
,
158 .num_gpi_regs
= NUM_GPIO_COM2_GPI_REGS
,
159 .pad_cfg_base
= PAD_CFG_BASE
,
160 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
161 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
162 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
163 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
164 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
165 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
167 .acpi_path
= "\\_SB.PCI0.GPIO",
168 .reset_map
= rst_map
,
169 .num_reset_vals
= ARRAY_SIZE(rst_map
),
170 .groups
= lewisburg_community2_groups
,
171 .num_groups
= ARRAY_SIZE(lewisburg_community2_groups
),
175 const struct pad_community
*soc_gpio_get_community(size_t *num_communities
)
177 *num_communities
= ARRAY_SIZE(lewisburg_gpio_communities
);
178 return lewisburg_gpio_communities
;
181 const struct pmc_to_gpio_route
*soc_pmc_gpio_routes(size_t *num
)
183 static const struct pmc_to_gpio_route routes
[] = {
196 *num
= ARRAY_SIZE(routes
);