src/soc/intel/xeon_sp/skx/soc_util.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <hob_iiouds.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <intelblocks/pcr.h>
  10 #include <soc/iomap.h>
  11 #include <soc/msr.h>
  12 #include <soc/pci_devs.h>
  13 #include <soc/pcr_ids.h>
  14 #include <soc/soc_util.h>
  15 #include <soc/util.h>
  16
  17
  18 /*
  19  *     +-------------------------+  TOLM
  20  *     | System Management Mode  |
  21  *     |      code and data      |
  22  *     |         (TSEG)          |
  23  *     +-------------------------+  SMM base (aligned)
  24  *     |                         |
  25  *     | Chipset Reserved Memory |
  26  *     |                         |
  27  *     +-------------------------+  top_of_ram (aligned)
  28  *     |                         |
  29  *     |       CBMEM Root        |
  30  *     |                         |
  31  *     +-------------------------+
  32  *     |                         |
  33  *     |   FSP Reserved Memory   |
  34  *     |                         |
  35  *     +-------------------------+
  36  *     |                         |
  37  *     |  Various CBMEM Entries  |
  38  *     |                         |
  39  *     +-------------------------+  top_of_stack (8 byte aligned)
  40  *     |                         |
  41  *     |   stack (CBMEM Entry)   |
  42  *     |                         |
  43  *     +-------------------------+
  44  */
  45
  46 const struct SystemMemoryMapHob *get_system_memory_map(void)
  47 {
  48         size_t hob_size;
  49         const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
  50         const struct SystemMemoryMapHob *memmap_addr;
  51
  52         memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
  53         assert(memmap_addr && hob_size != 0);
  54
  55         return memmap_addr;
  56 }
  57
  58 bool is_pcie_iio_stack_res(const STACK_RES *res)
  59 {
  60         return res->BusBase < res->BusLimit;
  61 }
  62
  63 bool is_ubox_stack_res(const STACK_RES *res)
  64 {
  65         /*
  66          * Unlike on later platforms there's no separate "UBOX" stack.
  67          *
  68          * The UBOX devices can always be found on the first bus on the stack IIO0 (CSTACK).
  69          * This bus is also referred to as uncore bus 0 or B(30).
  70          * It has at a fixed address the UBOX:
  71          * B(30):8.0 8086:2014
  72          * B(30):8.1 8086:2015
  73          * B(30):8.2 8086:2016
  74          *
  75          * The PCU devices can always be on the first bus of the stack IIO1 (PSTACK).
  76          * This bus is also referred to as uncore bus 1 or B(31).
  77          * It has at a fixed address the PCU:
  78          * B(31):30.0 8086:2080
  79          * B(31):30.1 8086:2081
  80          * B(31):30.2 8086:2082
  81          */
  82
  83         return false;
  84 }
  85
  86 /* Returns the UBOX(stack) bus number when called from socket0 */
  87 uint8_t socket0_get_ubox_busno(const uint8_t stack)
  88 {
  89         if (stack >= MAX_IIO_STACK) {
  90                 printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
  91                 return 0;
  92         }
  93         const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
  94         const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
  95         return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
  96 }
  97
  98 #if ENV_RAMSTAGE
  99 void config_reset_cpl3_csrs(void)
 100 {
 101         uint32_t data, plat_info, max_min_turbo_limit_ratio;
 102         struct device *dev;
 103
 104         dev = NULL;
 105         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
 106                 data = pci_read_config32(dev, PCU_CR0_P_STATE_LIMITS);
 107                 data |= P_STATE_LIMITS_LOCK;
 108                 pci_write_config32(dev, PCU_CR0_P_STATE_LIMITS, data);
 109
 110                 plat_info = pci_read_config32(dev, PCU_CR0_PLATFORM_INFO);
 111                 dump_csr64(dev, PCU_CR0_PLATFORM_INFO);
 112                 max_min_turbo_limit_ratio =
 113                         (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
 114                                 MAX_NON_TURBO_LIM_RATIO_SHIFT;
 115                 printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
 116                         plat_info, max_min_turbo_limit_ratio);
 117         }
 118
 119         dev = NULL;
 120         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
 121                 data = pci_read_config32(dev, PCU_CR1_SAPMCTL);
 122                 /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
 123                 data &= 0x0fffffff;
 124                 data |= SAPMCTL_LOCK_MASK;
 125                 pci_write_config32(dev, PCU_CR1_SAPMCTL, data);
 126         }
 127
 128         dev = NULL;
 129         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
 130                 data = PCIE_IN_PKGCSTATE_L1_MASK;
 131                 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
 132
 133                 data = KTI_IN_PKGCSTATE_L1_MASK;
 134                 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
 135
 136                 data = PROCHOT_RATIO;
 137                 printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
 138                 pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
 139                 dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
 140
 141                 data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
 142                 data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
 143                 pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
 144         }
 145 }
 146 #endif
 147
 148 /*
 149  * EX: SKX-SP
 150  * Ports    Stack   Stack(HOB)  IioConfigIou
 151  * ==========================================
 152  * 0        CSTACK      stack 0     IOU0
 153  * 1A..1D   PSTACKZ     stack 1     IOU1
 154  * 2A..2D   PSTACK1     stack 2     IOU2
 155  * 3A..3D   PSTACK2     stack 3     IOU3
 156  * 5A..4D   PSTACK3     stack 4     IOU4
 157  * 5A..5D   PSTACK4     stack 5     IOU5
 158  */
 159 int soc_get_stack_for_port(int port)
 160 {
 161         if (port == PORT_0)
 162                 return CSTACK;
 163         else if (port >= PORT_1A && port <= PORT_1D)
 164                 return PSTACK0;
 165         else if (port >= PORT_2A && port <= PORT_2D)
 166                 return PSTACK1;
 167         else if (port >= PORT_3A && port <= PORT_3D)
 168                 return PSTACK2;
 169         else if (port >= PORT_4A && port <= PORT_4D)
 170                 return PSTACK3; // MCP0
 171         else if (port >= PORT_5A && port <= PORT_5D)
 172                 return PSTACK4; // MCP1
 173         else
 174                 return -1;
 175 }
 176
 177 uint8_t soc_get_iio_ioapicid(int socket, int stack)
 178 {
 179         uint8_t ioapic_id = socket ? 0xf : 0x9;
 180         switch (stack) {
 181         case CSTACK:
 182                 break;
 183         case PSTACK0:
 184                 ioapic_id += 1;
 185                 break;
 186         case PSTACK1:
 187                 ioapic_id += 2;
 188                 break;
 189         case PSTACK2:
 190                 ioapic_id += 3;
 191                 break;
 192         default:
 193                 return 0xff;
 194         }
 195         return ioapic_id;
 196 }
 197
 198 bool is_memtype_reserved(uint16_t mem_type)
 199 {
 200         return !!(mem_type & MEM_TYPE_RESERVED);
 201 }
 202
 203 bool is_memtype_non_volatile(uint16_t mem_type)
 204 {
 205         return !(mem_type & MEMTYPE_VOLATILE_MASK);
 206 }
 207
 208 bool is_memtype_processor_attached(uint16_t mem_type)
 209 {
 210         return true;
 211 }
 212
 213 uint8_t get_cxl_node_count(void)
 214 {
 215         return 0;
 216 }
 217
 218 bool get_mmio_high_base_size(resource_t *base, resource_t *size)
 219 {
 220         return false;
 221 }