1 /* SPDX-License-Identifier: GPL-2.0-only */
7 #include <intelblocks/cfg.h>
12 #define MAX_PCH_PCIE_PORT 20
16 ForceEnable - Enable/Disable PCH PCIe port
17 PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
19 struct pch_pcie_port
{
21 uint8_t PortLinkSpeed
;
24 struct soc_intel_xeon_sp_spr_config
{
25 /* Common struct containing soc config data required by common code */
26 struct soc_intel_common_config common_soc_config
;
28 /* Struct for configuring PCH PCIe port */
29 struct pch_pcie_port pch_pci_port
[MAX_PCH_PCIE_PORT
];
32 * Device Interrupt Polarity Control
33 * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
34 * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
35 * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
36 * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
43 uint64_t turbo_ratio_limit
;
44 uint64_t turbo_ratio_limit_cores
;
46 uint32_t pstate_req_ratio
;
50 /* Generic IO decode ranges */
56 /* TCC activation offset */
59 enum acpi_cstate_mode cstate_states
;
62 typedef struct soc_intel_xeon_sp_spr_config config_t
;