mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2
[coreboot2.git] / src / soc / intel / xeon_sp / spr / chip.h
blob28af550e3ac01ff323c8115eadceca16662be656
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _SOC_CHIP_H_
4 #define _SOC_CHIP_H_
6 #include <gpio.h>
7 #include <intelblocks/cfg.h>
8 #include <soc/acpi.h>
9 #include <soc/irq.h>
10 #include <stdint.h>
12 #define MAX_PCH_PCIE_PORT 20
14 /**
15 UPD_PCH_PCIE_PORT:
16 ForceEnable - Enable/Disable PCH PCIe port
17 PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
18 **/
19 struct pch_pcie_port {
20 uint8_t ForceEnable;
21 uint8_t PortLinkSpeed;
24 struct soc_intel_xeon_sp_spr_config {
25 /* Common struct containing soc config data required by common code */
26 struct soc_intel_common_config common_soc_config;
28 /* Struct for configuring PCH PCIe port */
29 struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT];
31 /**
32 * Device Interrupt Polarity Control
33 * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
34 * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
35 * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
36 * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
38 uint32_t ipc0;
39 uint32_t ipc1;
40 uint32_t ipc2;
41 uint32_t ipc3;
43 uint64_t turbo_ratio_limit;
44 uint64_t turbo_ratio_limit_cores;
46 uint32_t pstate_req_ratio;
48 uint8_t vtd_support;
50 /* Generic IO decode ranges */
51 uint32_t gen1_dec;
52 uint32_t gen2_dec;
53 uint32_t gen3_dec;
54 uint32_t gen4_dec;
56 /* TCC activation offset */
57 uint32_t tcc_offset;
59 enum acpi_cstate_mode cstate_states;
62 typedef struct soc_intel_xeon_sp_spr_config config_t;
64 #endif