?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
soc/intel: Remove blank lines before '}' and after '{'
[coreboot2.git] / src / lib / reg_script.c
blobbad9d9c53e6638c8ac5c8afd505da4a26c92f47c
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <device/device.h>
8 #include <device/resource.h>
9 #include <device/pci.h>
10 #include <stdint.h>
11 #include <reg_script.h>
12
13 #if ENV_X86
14 #include <cpu/x86/msr.h>
15 #endif
16
17 #if ENV_X86
18 #include <arch/io.h>
19 #define HAS_ARCH_IO 1
20 #else
21 #define HAS_ARCH_IO 0
22 #endif
23
24 #define HAS_IOSF (CONFIG(SOC_INTEL_BAYTRAIL))
25
26 #if HAS_IOSF
27 #include <soc/iosf.h> /* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
28 #endif
29
30 #define POLL_DELAY 100 /* 100us */
31
32 #ifdef __SIMPLE_DEVICE__
33 #define EMPTY_DEV 0
34 #else
35 #define EMPTY_DEV NULL
36 #endif
37
38 #ifdef __SIMPLE_DEVICE__
39 static inline void reg_script_set_dev(struct reg_script_context *ctx,
40 pci_devfn_t dev)
41 #else
42 static inline void reg_script_set_dev(struct reg_script_context *ctx,
43 struct device *dev)
44 #endif
45 {
46 ctx->dev = dev;
47 ctx->res = NULL;
48 }
49
50 static inline void reg_script_set_step(struct reg_script_context *ctx,
51 const struct reg_script *step)
52 {
53 ctx->step = step;
54 }
55
56 static inline const struct reg_script *
57 reg_script_get_step(struct reg_script_context *ctx)
58 {
59 return ctx->step;
60 }
61
62 static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
63 {
64 #ifdef __SIMPLE_DEVICE__
65 return NULL;
66 #else
67 struct resource *res;
68 const struct reg_script *step = reg_script_get_step(ctx);
69
70 res = ctx->res;
71
72 if (res != NULL && res->index == step->res_index)
73 return res;
74
75 res = find_resource(ctx->dev, step->res_index);
76 ctx->res = res;
77 return res;
78 #endif
79 }
80
81 static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
82 {
83 const struct reg_script *step = reg_script_get_step(ctx);
84
85 switch (step->size) {
86 case REG_SCRIPT_SIZE_8:
87 return pci_read_config8(ctx->dev, step->reg);
88 case REG_SCRIPT_SIZE_16:
89 return pci_read_config16(ctx->dev, step->reg);
90 case REG_SCRIPT_SIZE_32:
91 return pci_read_config32(ctx->dev, step->reg);
92 }
93 return 0;
94 }
95
96 static void reg_script_write_pci(struct reg_script_context *ctx)
97 {
98 const struct reg_script *step = reg_script_get_step(ctx);
99
100 switch (step->size) {
101 case REG_SCRIPT_SIZE_8:
102 pci_write_config8(ctx->dev, step->reg, step->value);
103 break;
104 case REG_SCRIPT_SIZE_16:
105 pci_write_config16(ctx->dev, step->reg, step->value);
106 break;
107 case REG_SCRIPT_SIZE_32:
108 pci_write_config32(ctx->dev, step->reg, step->value);
109 break;
110 }
111 }
112
113 #if HAS_ARCH_IO
114 static uint32_t reg_script_read_io(struct reg_script_context *ctx)
115 {
116 const struct reg_script *step = reg_script_get_step(ctx);
117
118 switch (step->size) {
119 case REG_SCRIPT_SIZE_8:
120 return inb(step->reg);
121 case REG_SCRIPT_SIZE_16:
122 return inw(step->reg);
123 case REG_SCRIPT_SIZE_32:
124 return inl(step->reg);
125 }
126 return 0;
127 }
128
129 static void reg_script_write_io(struct reg_script_context *ctx)
130 {
131 const struct reg_script *step = reg_script_get_step(ctx);
132
133 switch (step->size) {
134 case REG_SCRIPT_SIZE_8:
135 outb(step->value, step->reg);
136 break;
137 case REG_SCRIPT_SIZE_16:
138 outw(step->value, step->reg);
139 break;
140 case REG_SCRIPT_SIZE_32:
141 outl(step->value, step->reg);
142 break;
143 }
144 }
145 #endif
146
147 static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
148 {
149 const struct reg_script *step = reg_script_get_step(ctx);
150
151 switch (step->size) {
152 case REG_SCRIPT_SIZE_8:
153 return read8((u8 *)(uintptr_t)step->reg);
154 case REG_SCRIPT_SIZE_16:
155 return read16((u16 *)(uintptr_t)step->reg);
156 case REG_SCRIPT_SIZE_32:
157 return read32((u32 *)(uintptr_t)step->reg);
158 }
159 return 0;
160 }
161
162 static void reg_script_write_mmio(struct reg_script_context *ctx)
163 {
164 const struct reg_script *step = reg_script_get_step(ctx);
165
166 switch (step->size) {
167 case REG_SCRIPT_SIZE_8:
168 write8((u8 *)(uintptr_t)step->reg, step->value);
169 break;
170 case REG_SCRIPT_SIZE_16:
171 write16((u16 *)(uintptr_t)step->reg, step->value);
172 break;
173 case REG_SCRIPT_SIZE_32:
174 write32((u32 *)(uintptr_t)step->reg, step->value);
175 break;
176 }
177 }
178
179 static uint32_t reg_script_read_res(struct reg_script_context *ctx)
180 {
181 struct resource *res;
182 uint32_t val = 0;
183 const struct reg_script *step = reg_script_get_step(ctx);
184
185 res = reg_script_get_resource(ctx);
186
187 if (res == NULL)
188 return val;
189
190 if (res->flags & IORESOURCE_IO) {
191 const struct reg_script io_step = {
192 .size = step->size,
193 .reg = res->base + step->reg,
194 };
195 reg_script_set_step(ctx, &io_step);
196 val = reg_script_read_io(ctx);
197 } else if (res->flags & IORESOURCE_MEM) {
198 const struct reg_script mmio_step = {
199 .size = step->size,
200 .reg = res->base + step->reg,
201 };
202 reg_script_set_step(ctx, &mmio_step);
203 val = reg_script_read_mmio(ctx);
204 }
205 reg_script_set_step(ctx, step);
206 return val;
207 }
208
209 static void reg_script_write_res(struct reg_script_context *ctx)
210 {
211 struct resource *res;
212 const struct reg_script *step = reg_script_get_step(ctx);
213
214 res = reg_script_get_resource(ctx);
215
216 if (res == NULL)
217 return;
218
219 if (res->flags & IORESOURCE_IO) {
220 const struct reg_script io_step = {
221 .size = step->size,
222 .reg = res->base + step->reg,
223 .value = step->value,
224 };
225 reg_script_set_step(ctx, &io_step);
226 reg_script_write_io(ctx);
227 } else if (res->flags & IORESOURCE_MEM) {
228 const struct reg_script mmio_step = {
229 .size = step->size,
230 .reg = res->base + step->reg,
231 .value = step->value,
232 };
233 reg_script_set_step(ctx, &mmio_step);
234 reg_script_write_mmio(ctx);
235 }
236 reg_script_set_step(ctx, step);
237 }
238
239 #if HAS_IOSF
240 static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
241 {
242 const struct reg_script *step = reg_script_get_step(ctx);
243
244 switch (step->id) {
245 case IOSF_PORT_AUNIT:
246 return iosf_aunit_read(step->reg);
247 case IOSF_PORT_CPU_BUS:
248 return iosf_cpu_bus_read(step->reg);
249 case IOSF_PORT_BUNIT:
250 return iosf_bunit_read(step->reg);
251 case IOSF_PORT_DUNIT_CH0:
252 return iosf_dunit_ch0_read(step->reg);
253 case IOSF_PORT_PMC:
254 return iosf_punit_read(step->reg);
255 case IOSF_PORT_USBPHY:
256 return iosf_usbphy_read(step->reg);
257 case IOSF_PORT_SEC:
258 return iosf_sec_read(step->reg);
259 case IOSF_PORT_0x45:
260 return iosf_port45_read(step->reg);
261 case IOSF_PORT_0x46:
262 return iosf_port46_read(step->reg);
263 case IOSF_PORT_0x47:
264 return iosf_port47_read(step->reg);
265 case IOSF_PORT_SCORE:
266 return iosf_score_read(step->reg);
267 case IOSF_PORT_0x55:
268 return iosf_port55_read(step->reg);
269 case IOSF_PORT_0x58:
270 return iosf_port58_read(step->reg);
271 case IOSF_PORT_0x59:
272 return iosf_port59_read(step->reg);
273 case IOSF_PORT_0x5a:
274 return iosf_port5a_read(step->reg);
275 case IOSF_PORT_USHPHY:
276 return iosf_ushphy_read(step->reg);
277 case IOSF_PORT_SCC:
278 return iosf_scc_read(step->reg);
279 case IOSF_PORT_LPSS:
280 return iosf_lpss_read(step->reg);
281 case IOSF_PORT_0xa2:
282 return iosf_porta2_read(step->reg);
283 case IOSF_PORT_CCU:
284 return iosf_ccu_read(step->reg);
285 case IOSF_PORT_SSUS:
286 return iosf_ssus_read(step->reg);
287 default:
288 printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
289 step->id);
290 break;
291 }
292 return 0;
293 }
294
295 static void reg_script_write_iosf(struct reg_script_context *ctx)
296 {
297 const struct reg_script *step = reg_script_get_step(ctx);
298
299 switch (step->id) {
300 case IOSF_PORT_AUNIT:
301 iosf_aunit_write(step->reg, step->value);
302 break;
303 case IOSF_PORT_CPU_BUS:
304 iosf_cpu_bus_write(step->reg, step->value);
305 break;
306 case IOSF_PORT_BUNIT:
307 iosf_bunit_write(step->reg, step->value);
308 break;
309 case IOSF_PORT_DUNIT_CH0:
310 iosf_dunit_write(step->reg, step->value);
311 break;
312 case IOSF_PORT_PMC:
313 iosf_punit_write(step->reg, step->value);
314 break;
315 case IOSF_PORT_USBPHY:
316 iosf_usbphy_write(step->reg, step->value);
317 break;
318 case IOSF_PORT_SEC:
319 iosf_sec_write(step->reg, step->value);
320 break;
321 case IOSF_PORT_0x45:
322 iosf_port45_write(step->reg, step->value);
323 break;
324 case IOSF_PORT_0x46:
325 iosf_port46_write(step->reg, step->value);
326 break;
327 case IOSF_PORT_0x47:
328 iosf_port47_write(step->reg, step->value);
329 break;
330 case IOSF_PORT_SCORE:
331 iosf_score_write(step->reg, step->value);
332 break;
333 case IOSF_PORT_0x55:
334 iosf_port55_write(step->reg, step->value);
335 break;
336 case IOSF_PORT_0x58:
337 iosf_port58_write(step->reg, step->value);
338 break;
339 case IOSF_PORT_0x59:
340 iosf_port59_write(step->reg, step->value);
341 break;
342 case IOSF_PORT_0x5a:
343 iosf_port5a_write(step->reg, step->value);
344 break;
345 case IOSF_PORT_USHPHY:
346 iosf_ushphy_write(step->reg, step->value);
347 break;
348 case IOSF_PORT_SCC:
349 iosf_scc_write(step->reg, step->value);
350 break;
351 case IOSF_PORT_LPSS:
352 iosf_lpss_write(step->reg, step->value);
353 break;
354 case IOSF_PORT_0xa2:
355 iosf_porta2_write(step->reg, step->value);
356 break;
357 case IOSF_PORT_CCU:
358 iosf_ccu_write(step->reg, step->value);
359 break;
360 case IOSF_PORT_SSUS:
361 iosf_ssus_write(step->reg, step->value);
362 break;
363 default:
364 printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
365 step->id);
366 break;
367 }
368 }
369 #endif /* HAS_IOSF */
370
371
372 static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
373 {
374 #if ENV_X86
375 const struct reg_script *step = reg_script_get_step(ctx);
376 msr_t msr = rdmsr(step->reg);
377 uint64_t value = msr.hi;
378 value <<= 32;
379 value |= msr.lo;
380 return value;
381 #endif
382 }
383
384 static void reg_script_write_msr(struct reg_script_context *ctx)
385 {
386 #if ENV_X86
387 const struct reg_script *step = reg_script_get_step(ctx);
388 msr_t msr;
389 msr.hi = step->value >> 32;
390 msr.lo = step->value & 0xffffffff;
391 wrmsr(step->reg, msr);
392 #endif
393 }
394
395 /* Locate the structure containing the platform specific bus access routines */
396 static const struct reg_script_bus_entry
397 *find_bus(const struct reg_script *step)
398 {
399 extern const struct reg_script_bus_entry *_rsbe_init_begin[];
400 extern const struct reg_script_bus_entry *_ersbe_init_begin[];
401 const struct reg_script_bus_entry * const *bus;
402 size_t table_entries;
403 size_t i;
404
405 /* Locate the platform specific bus */
406 bus = _rsbe_init_begin;
407 table_entries = &_ersbe_init_begin[0] - &_rsbe_init_begin[0];
408 for (i = 0; i < table_entries; i++) {
409 if (bus[i]->type == step->type)
410 return bus[i];
411 }
412
413 /* Bus not found */
414 return NULL;
415 }
416
417 static void reg_script_display(struct reg_script_context *ctx,
418 const struct reg_script *step, const char *arrow, uint64_t value)
419 {
420 /* Display the register address and data */
421 if (ctx->display_prefix != NULL)
422 printk(BIOS_INFO, "%s: ", ctx->display_prefix);
423 if (ctx->display_features & REG_SCRIPT_DISPLAY_REGISTER)
424 printk(BIOS_INFO, "0x%08x %s ", step->reg, arrow);
425 if (ctx->display_features & REG_SCRIPT_DISPLAY_VALUE)
426 switch (step->size) {
427 case REG_SCRIPT_SIZE_8:
428 printk(BIOS_INFO, "0x%02x\n", (uint8_t)value);
429 break;
430 case REG_SCRIPT_SIZE_16:
431 printk(BIOS_INFO, "0x%04x\n", (int16_t)value);
432 break;
433 case REG_SCRIPT_SIZE_32:
434 printk(BIOS_INFO, "0x%08x\n", (uint32_t)value);
435 break;
436 default:
437 printk(BIOS_INFO, "0x%016llx\n", value);
438 break;
439 }
440 }
441
442 static uint64_t reg_script_read(struct reg_script_context *ctx)
443 {
444 const struct reg_script *step = reg_script_get_step(ctx);
445 uint64_t value = 0;
446
447 switch (step->type) {
448 case REG_SCRIPT_TYPE_PCI:
449 ctx->display_prefix = "PCI";
450 value = reg_script_read_pci(ctx);
451 break;
452 #if HAS_ARCH_IO
453 case REG_SCRIPT_TYPE_IO:
454 ctx->display_prefix = "IO";
455 value = reg_script_read_io(ctx);
456 break;
457 #endif
458 case REG_SCRIPT_TYPE_MMIO:
459 ctx->display_prefix = "MMIO";
460 value = reg_script_read_mmio(ctx);
461 break;
462 case REG_SCRIPT_TYPE_RES:
463 ctx->display_prefix = "RES";
464 value = reg_script_read_res(ctx);
465 break;
466 case REG_SCRIPT_TYPE_MSR:
467 ctx->display_prefix = "MSR";
468 value = reg_script_read_msr(ctx);
469 break;
470 #if HAS_IOSF
471 case REG_SCRIPT_TYPE_IOSF:
472 ctx->display_prefix = "IOSF";
473 value = reg_script_read_iosf(ctx);
474 break;
475 #endif /* HAS_IOSF */
476 default:
477 {
478 const struct reg_script_bus_entry *bus;
479
480 /* Read from the platform specific bus */
481 bus = find_bus(step);
482 if (bus != NULL) {
483 value = bus->reg_script_read(ctx);
484 break;
485 }
486 }
487 printk(BIOS_ERR,
488 "Unsupported read type (0x%x) for this device!\n",
489 step->type);
490 return 0;
491 }
492
493 /* Display the register address and data */
494 if (ctx->display_features)
495 reg_script_display(ctx, step, "-->", value);
496 return value;
497 }
498
499 static void reg_script_write(struct reg_script_context *ctx)
500 {
501 const struct reg_script *step = reg_script_get_step(ctx);
502
503 switch (step->type) {
504 case REG_SCRIPT_TYPE_PCI:
505 ctx->display_prefix = "PCI";
506 reg_script_write_pci(ctx);
507 break;
508 #if HAS_ARCH_IO
509 case REG_SCRIPT_TYPE_IO:
510 ctx->display_prefix = "IO";
511 reg_script_write_io(ctx);
512 break;
513 #endif
514 case REG_SCRIPT_TYPE_MMIO:
515 ctx->display_prefix = "MMIO";
516 reg_script_write_mmio(ctx);
517 break;
518 case REG_SCRIPT_TYPE_RES:
519 ctx->display_prefix = "RES";
520 reg_script_write_res(ctx);
521 break;
522 case REG_SCRIPT_TYPE_MSR:
523 ctx->display_prefix = "MSR";
524 reg_script_write_msr(ctx);
525 break;
526 #if HAS_IOSF
527 case REG_SCRIPT_TYPE_IOSF:
528 ctx->display_prefix = "IOSF";
529 reg_script_write_iosf(ctx);
530 break;
531 #endif /* HAS_IOSF */
532 default:
533 {
534 const struct reg_script_bus_entry *bus;
535
536 /* Write to the platform specific bus */
537 bus = find_bus(step);
538 if (bus != NULL) {
539 bus->reg_script_write(ctx);
540 break;
541 }
542 }
543 printk(BIOS_ERR,
544 "Unsupported write type (0x%x) for this device!\n",
545 step->type);
546 return;
547 }
548
549 /* Display the register address and data */
550 if (ctx->display_features)
551 reg_script_display(ctx, step, "<--", step->value);
552 }
553
554 static void reg_script_rmw(struct reg_script_context *ctx)
555 {
556 uint64_t value;
557 const struct reg_script *step = reg_script_get_step(ctx);
558 struct reg_script write_step = *step;
559
560 value = reg_script_read(ctx);
561 value &= step->mask;
562 value |= step->value;
563 write_step.value = value;
564 reg_script_set_step(ctx, &write_step);
565 reg_script_write(ctx);
566 reg_script_set_step(ctx, step);
567 }
568
569 static void reg_script_rxw(struct reg_script_context *ctx)
570 {
571 uint64_t value;
572 const struct reg_script *step = reg_script_get_step(ctx);
573 struct reg_script write_step = *step;
574
575 /*
576 * XOR logic table
577 * Input XOR Value
578 * 0 0 0
579 * 0 1 1
580 * 1 0 1
581 * 1 1 0
582 *
583 * Supported operations
584 *
585 * Input Mask Temp XOR Value Operation
586 * 0 0 0 0 0 Clear bit
587 * 1 0 0 0 0
588 * 0 0 0 1 1 Set bit
589 * 1 0 0 1 1
590 * 0 1 0 0 0 Preserve bit
591 * 1 1 1 0 1
592 * 0 1 0 1 1 Toggle bit
593 * 1 1 1 1 0
594 */
595 value = reg_script_read(ctx);
596 value &= step->mask;
597 value ^= step->value;
598 write_step.value = value;
599 reg_script_set_step(ctx, &write_step);
600 reg_script_write(ctx);
601 reg_script_set_step(ctx, step);
602 }
603
604 /* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
605 * as recursive call with a new context that has the same dev and resource
606 * as the previous one. That will run to completion and then move on to the
607 * next step of the previous context. */
608 static void reg_script_run_next(struct reg_script_context *ctx,
609 const struct reg_script *step);
610
611
612 static void reg_script_run_step(struct reg_script_context *ctx,
613 const struct reg_script *step)
614 {
615 uint64_t value = 0, try;
616
617 ctx->display_features = ctx->display_state;
618 ctx->display_prefix = NULL;
619 switch (step->command) {
620 case REG_SCRIPT_COMMAND_READ:
621 (void)reg_script_read(ctx);
622 break;
623 case REG_SCRIPT_COMMAND_WRITE:
624 reg_script_write(ctx);
625 break;
626 case REG_SCRIPT_COMMAND_RMW:
627 reg_script_rmw(ctx);
628 break;
629 case REG_SCRIPT_COMMAND_RXW:
630 reg_script_rxw(ctx);
631 break;
632 case REG_SCRIPT_COMMAND_POLL:
633 for (try = 0; try < step->timeout; try += POLL_DELAY) {
634 value = reg_script_read(ctx) & step->mask;
635 if (value == step->value)
636 break;
637 udelay(POLL_DELAY);
638 }
639 if (try >= step->timeout)
640 printk(BIOS_WARNING, "%s: POLL timeout waiting for "
641 "0x%x to be 0x%lx, got 0x%lx\n", __func__,
642 step->reg, (unsigned long)step->value,
643 (unsigned long)value);
644 break;
645 case REG_SCRIPT_COMMAND_SET_DEV:
646 reg_script_set_dev(ctx, step->dev);
647 break;
648 case REG_SCRIPT_COMMAND_NEXT:
649 reg_script_run_next(ctx, step->next);
650 break;
651 case REG_SCRIPT_COMMAND_DISPLAY:
652 ctx->display_state = step->value;
653 break;
654
655 default:
656 printk(BIOS_WARNING, "Invalid command: %08x\n",
657 step->command);
658 break;
659 }
660 }
661
662 static void reg_script_run_with_context(struct reg_script_context *ctx)
663 {
664 while (1) {
665 const struct reg_script *step = reg_script_get_step(ctx);
666
667 if (step->command == REG_SCRIPT_COMMAND_END)
668 break;
669
670 reg_script_run_step(ctx, step);
671 reg_script_set_step(ctx, step + 1);
672 }
673 }
674
675 static void reg_script_run_next(struct reg_script_context *prev_ctx,
676 const struct reg_script *step)
677 {
678 struct reg_script_context ctx;
679
680 /* Use prev context as a basis but start at a new step. */
681 ctx = *prev_ctx;
682 reg_script_set_step(&ctx, step);
683 reg_script_run_with_context(&ctx);
684 }
685
686 #ifdef __SIMPLE_DEVICE__
687 void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step)
688 #else
689 void reg_script_run_on_dev(struct device *dev, const struct reg_script *step)
690 #endif
691 {
692 struct reg_script_context ctx;
693
694 ctx.display_state = REG_SCRIPT_DISPLAY_NOTHING;
695 reg_script_set_dev(&ctx, dev);
696 reg_script_set_step(&ctx, step);
697 reg_script_run_with_context(&ctx);
698 }
699
700 void reg_script_run(const struct reg_script *step)
701 {
702 reg_script_run_on_dev(EMPTY_DEV, step);
703 }
coreboot repo mirror