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soc/intel: Remove blank lines before '}' and after '{'
[coreboot2.git] / src / mainboard / acer / aspire_vn7_572g / devicetree.cb
blob0328ec7244c0f5ed0220fb53a1798c19c22d2c52
1 ## SPDX-License-Identifier: GPL-2.0-only
2
3 chip soc/intel/skylake
4
5 # Intel Common SoC Config
6 #+-------------------+---------------------------+
7 #| Field | Value |
8 #+-------------------+---------------------------+
9 #| I2C0 | Touchscreen |
10 #| I2C1 | Touchpad |
11 #+-------------------+---------------------------+
12 register "common_soc_config" = "{
13 .i2c[0] = {
14 .speed = I2C_SPEED_FAST,
15 },
16 .i2c[1] = {
17 .speed = I2C_SPEED_FAST,
18 .speed_config[0] = {
19 .speed = I2C_SPEED_FAST,
20 .scl_lcnt = 128,
21 .scl_hcnt = 160,
22 .sda_hold = 30,
23 }
24 },
25 }"
26
27 # TODO: Drop once CB:55224 is merged
28 register "SerialIoDevMode" = "{
29 [PchSerialIoIndexI2C0] = PchSerialIoPci,
30 [PchSerialIoIndexI2C1] = PchSerialIoPci,
31 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
32 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
33 }"
34
35 device cpu_cluster 0 on end
36 device domain 0 on
37 subsystemid 0x1025 0x1037 inherit
38 device ref system_agent on
39 # Enable "Enhanced Intel SpeedStep"
40 register "eist_enable" = "1"
41
42 # Set the Thermal Control Circuit (TCC) activation value to 97C
43 # even though FSP integration guide says to set it to 100C for SKL-U
44 # (offset at 0), because when the TCC activates at 100C, the CPU
45 # will have already shut itself down from overheating protection.
46 register "tcc_offset" = "3" # TCC of 97C
47
48 register "SaGv" = "SaGv_Enabled"
49
50 # VR Slew rate setting for improving audible noise
51 register "AcousticNoiseMitigation" = "1"
52 register "SlowSlewRateForIa" = "3" # Fast/16
53 register "SlowSlewRateForGt" = "3" # Fast/16
54 register "SlowSlewRateForSa" = "0" # Fast/2
55 register "FastPkgCRampDisableIa" = "0"
56 register "FastPkgCRampDisableGt" = "0"
57 register "FastPkgCRampDisableSa" = "0"
58
59 # PL1, PL2 override 35W, PL4 override 43W
60 register "power_limits_config" = "{
61 .tdp_pl1_override = 35,
62 .tdp_pl2_override = 35,
63 .tdp_pl4 = 43,
64 }"
65
66 # ISL95857 VR
67 # Send VR specific command for PS4 exit issue
68 register "SendVrMbxCmd" = "2"
69 # Send VR mailbox command for IA/GT/SA rails
70 register "IslVrCmd" = "2"
71 end
72 device ref igpu on
73 register "panel_cfg" = "{
74 .up_delay_ms = 150, // T3
75 .down_delay_ms = 50, // T10
76 .cycle_delay_ms = 500, // T12
77 .backlight_on_delay_ms = 1, // T7
78 .backlight_off_delay_ms = 200, // T9
79 .backlight_pwm_hz = 1000,
80 }"
81
82 # IGD Displays; LFP and 3*EFP
83 # FIXME: VBT does not define EFP3, board has no EFP2?
84 register "gfx" = "{
85 .use_spread_spectrum_clock = 1,
86 .ndid = 4, .did = { 0x0400, 0x0300, 0x0301, 0x0302 }
87 }"
88
89 register "PrimaryDisplay" = "Display_Switchable"
90 end
91 device ref south_xhci on
92 register "usb2_ports[0]" = "{
93 .enable = 1,
94 .ocpin = OC_SKIP,
95 .tx_bias = USB2_BIAS_17MV,
96 .tx_emp_enable = USB2_DE_EMP_ON,
97 .pre_emp_bias = USB2_BIAS_28MV,
98 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
99 }" # Type-A Port (right)
100 register "usb2_ports[1]" = "{
101 .enable = 1,
102 .ocpin = OC_SKIP,
103 .tx_bias = USB2_BIAS_17MV,
104 .tx_emp_enable = USB2_DE_EMP_ON,
105 .pre_emp_bias = USB2_BIAS_28MV,
106 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
107 }" # Type-A Port (right)
108 register "usb2_ports[2]" = "{
109 .enable = 1,
110 .ocpin = OC_SKIP,
111 .tx_bias = USB2_BIAS_17MV,
112 .tx_emp_enable = USB2_DE_EMP_ON,
113 .pre_emp_bias = USB2_BIAS_28MV,
114 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
115 }" # Type-C Port
116 register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A Port (left)
117 register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
118 register "usb2_ports[5]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchscreen
119 register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
120 register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
121 register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Finger-printer
122
123 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right); Capable of OTG
124 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
125 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
126 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
127 chip drivers/usb/acpi
128 register "desc" = ""Root Hub""
129 register "type" = "UPC_TYPE_HUB"
130 device usb 0.0 on
131 chip drivers/usb/acpi
132 register "desc" = ""USB2 Type-A Right""
133 register "type" = "UPC_TYPE_USB3_A"
134 register "group" = "ACPI_PLD_GROUP(0, 1)"
135 device usb 2.0 on end
136 end
137 chip drivers/usb/acpi
138 register "desc" = ""USB2 Type-A Right""
139 register "type" = "UPC_TYPE_USB3_A"
140 register "group" = "ACPI_PLD_GROUP(0, 2)"
141 device usb 2.1 on end
142 end
143 chip drivers/usb/acpi
144 register "desc" = ""USB2 Type-C""
145 register "type" = "UPC_TYPE_C_USB2_SS"
146 register "group" = "ACPI_PLD_GROUP(0, 3)"
147 device usb 2.2 on end
148 end
149 chip drivers/usb/acpi
150 register "desc" = ""USB2 Type-A Left""
151 register "type" = "UPC_TYPE_A"
152 register "group" = "ACPI_PLD_GROUP(0, 4)"
153 device usb 2.3 on end
154 end
155 chip drivers/usb/acpi
156 register "desc" = ""USB2 Bluetooth""
157 register "type" = "UPC_TYPE_UNUSED"
158 register "group" = "ACPI_PLD_GROUP(0, 5)"
159 device usb 2.4 on end
160 end
161 chip drivers/usb/acpi
162 register "desc" = ""USB2 Touchscreen""
163 register "type" = "UPC_TYPE_UNUSED"
164 register "group" = "ACPI_PLD_GROUP(0, 6)"
165 device usb 2.5 on end
166 end
167 chip drivers/usb/acpi
168 register "desc" = ""USB2 Webcam""
169 register "type" = "UPC_TYPE_UNUSED"
170 register "group" = "ACPI_PLD_GROUP(0, 7)"
171 device usb 2.6 on end
172 end
173 chip drivers/usb/acpi
174 register "desc" = ""USB2 SD""
175 register "type" = "UPC_TYPE_UNUSED"
176 register "group" = "ACPI_PLD_GROUP(0, 8)"
177 device usb 2.7 on end
178 end
179 chip drivers/usb/acpi
180 register "desc" = ""USB2 Finger-printer""
181 register "type" = "UPC_TYPE_UNUSED"
182 register "group" = "ACPI_PLD_GROUP(0, 9)"
183 device usb 2.8 on end
184 end
185 chip drivers/usb/acpi
186 register "desc" = ""USB3 Type-A Right""
187 register "type" = "UPC_TYPE_USB3_A"
188 register "group" = "ACPI_PLD_GROUP(0, 1)"
189 device usb 3.0 on end
190 end
191 chip drivers/usb/acpi
192 register "desc" = ""USB3 Type-A Right""
193 register "type" = "UPC_TYPE_USB3_A"
194 register "group" = "ACPI_PLD_GROUP(0, 2)"
195 device usb 3.1 on end
196 end
197 chip drivers/usb/acpi
198 register "desc" = ""USB3 Type-C""
199 register "type" = "UPC_TYPE_C_USB2_SS"
200 register "group" = "ACPI_PLD_GROUP(0, 3)"
201 device usb 3.2 on end
202 end
203 chip drivers/usb/acpi
204 register "desc" = ""USB3 Type-C""
205 register "type" = "UPC_TYPE_C_USB2_SS"
206 register "group" = "ACPI_PLD_GROUP(0, 3)"
207 device usb 3.3 on end
208 end
209 end
210 end
211 end
212 device ref thermal on end
213 device ref i2c0 on
214 chip drivers/i2c/hid
215 register "generic.name" = ""TPL0""
216 register "generic.hid" = ""ELAN2259""
217 register "generic.desc" = ""ELAN Touchscreen""
218 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
219 register "generic.device_present_gpio" = "GPP_B15"
220 register "hid_desc_reg_offset" = "0x01"
221 device i2c 0x10 on end
222 end
223 end
224 device ref i2c1 on
225 chip drivers/i2c/hid
226 register "generic.name" = ""TPD0""
227 register "generic.hid" = ""SYN1B7F""
228 register "generic.desc" = ""Synaptics Touchpad""
229 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
230 # register "generic.wake" = "GPE0_DW2_16" # FIXME: Use EC's GPE?
231 register "generic.detect" = "1"
232 register "hid_desc_reg_offset" = "0x20"
233 device i2c 0x2c on end
234 end
235 chip drivers/i2c/hid
236 register "generic.name" = ""TPD1""
237 register "generic.hid" = ""ELAN0501""
238 register "generic.desc" = ""ELAN Touchpad""
239 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
240 register "generic.detect" = "1"
241 register "hid_desc_reg_offset" = "0x01"
242 device i2c 0x15 on end
243 end
244 end
245 device ref heci1 on end
246 device ref sata on
247 register "SataMode" = "SATA_AHCI"
248 register "SataSalpSupport" = "1"
249 register "SataPortsEnable[1]" = "1" # HDD; BIT1 in 92h-93h
250 register "SataPortsEnable[2]" = "1" # ODD; BIT2 in 92h-93h
251 end
252 device ref uart2 on end
253 # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
254 device ref pcie_rp1 on
255 # dGPU; x4
256 register "PcieRpEnable[0]" = "1"
257 register "PcieRpAdvancedErrorReporting[0]" = "1"
258 register "PcieRpLtrEnable[0]" = "1"
259 register "PcieRpClkReqSupport[0]" = "1"
260 register "PcieRpClkReqNumber[0]" = "0"
261 register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
262 end
263 device ref pcie_rp7 on
264 # NGFF; x2
265 register "PcieRpEnable[6]" = "1"
266 register "PcieRpAdvancedErrorReporting[6]" = "1"
267 register "PcieRpLtrEnable[6]" = "1"
268 register "PcieRpClkReqSupport[6]" = "1"
269 register "PcieRpClkReqNumber[6]" = "3"
270 register "PcieRpMaxPayload[6]" = "RpMaxPayload_256"
271 end
272 device ref pcie_rp9 on
273 # LAN
274 register "PcieRpEnable[8]" = "1"
275 register "PcieRpAdvancedErrorReporting[8]" = "1"
276 register "PcieRpLtrEnable[8]" = "1"
277 register "PcieRpClkReqSupport[8]" = "1"
278 register "PcieRpClkReqNumber[8]" = "1"
279 register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
280 end
281 device ref pcie_rp10 on
282 # WLAN
283 register "PcieRpEnable[9]" = "1"
284 register "PcieRpAdvancedErrorReporting[9]" = "1"
285 register "PcieRpLtrEnable[9]" = "1"
286 register "PcieRpClkReqSupport[9]" = "1"
287 register "PcieRpClkReqNumber[9]" = "2"
288 register "PcieRpMaxPayload[9]" = "RpMaxPayload_256"
289 # ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
290 register "pcie_rp_aspm[9]" = "AspmL1"
291 end
292 # Although vendor's platform NVS area shows SCS is enabled, the SD card reader is actually connected over USB
293 device ref lpc_espi on
294 register "lpc_iod" = "0x0010" # 80h-81h; ComB: 2F8h-2FFh (COM 2)
295 register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_KBC_60_64
296 | LPC_IOE_EC_62_66 | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F" # 82h-83h
297 register "gen3_dec" = "0x00040069" # 8Ch-8Fh; EC (sideband): Port 68h/6Ch
298 register "gen4_dec" = "0x000c1201" # 90h-93h; EC (index): Port 1200h
299
300 # EC/KBC requires continuous mode
301 register "serirq_mode" = "SERIRQ_CONTINUOUS"
302 end
303 device ref pmc on
304 # Note that GPE events called out in ASL code rely on this
305 # route. i.e. If this route changes then the affected GPE
306 # offset bits also need to be changed.
307 register "gpe0_dw0" = "GPP_C" # 3:0 in pwrmbase+0120h
308 register "gpe0_dw1" = "GPP_D" # 7:4 in pwrmbase+0120h
309 register "gpe0_dw2" = "GPP_E" # 11:8 in pwrmbase+0120h
310
311 # Enable S0ix
312 register "s0ix_enable" = true
313
314 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h
315 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h
316 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h
317 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h
318 end
319 device ref hda on
320 register "DspEnable" = "1"
321 # PchHdaDspEndpointDmic is only to be returned to reference code
322 # DXE phase as HOB, used to select blob for NHLT
323 end
324 device ref smbus on end
325 device ref fast_spi on end
326 end
327 chip drivers/crb
328 device mmio 0xfed40000 on end
329 end
330 end
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