src/mainboard/amd/bilby/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/amd/picasso
   4         # ACP Configuration
   5         register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_I2S_TDM"
   6
   7         # Set FADT Configuration
   8         register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
   9         register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
  10
  11         register "has_usb2_phy_tune_params" = "1"
  12
  13         # Controller0 Port0 Default
  14         register "usb_2_port_tune_params[0]" = "{
  15                 .com_pds_tune = 0x03,
  16                 .sq_rx_tune = 0x3,
  17                 .tx_fsls_tune = 0x3,
  18                 .tx_pre_emp_amp_tune = 0x03,
  19                 .tx_pre_emp_pulse_tune = 0x0,
  20                 .tx_rise_tune = 0x1,
  21                 .tx_vref_tune = 0x6,
  22                 .tx_hsxv_tune = 0x3,
  23                 .tx_res_tune = 0x01,
  24         }"
  25
  26         # Controller0 Port1 Default
  27         register "usb_2_port_tune_params[1]" = "{
  28                 .com_pds_tune = 0x03,
  29                 .sq_rx_tune = 0x3,
  30                 .tx_fsls_tune = 0x3,
  31                 .tx_pre_emp_amp_tune = 0x03,
  32                 .tx_pre_emp_pulse_tune = 0x0,
  33                 .tx_rise_tune = 0x1,
  34                 .tx_vref_tune = 0x6,
  35                 .tx_hsxv_tune = 0x3,
  36                 .tx_res_tune = 0x01,
  37         }"
  38
  39         # Controller0 Port2 Default
  40         register "usb_2_port_tune_params[2]" = "{
  41                 .com_pds_tune = 0x03,
  42                 .sq_rx_tune = 0x3,
  43                 .tx_fsls_tune = 0x3,
  44                 .tx_pre_emp_amp_tune = 0x03,
  45                 .tx_pre_emp_pulse_tune = 0x0,
  46                 .tx_rise_tune = 0x1,
  47                 .tx_vref_tune = 0x6,
  48                 .tx_hsxv_tune = 0x3,
  49                 .tx_res_tune = 0x01,
  50         }"
  51
  52         # Controller0 Port3 Default
  53         register "usb_2_port_tune_params[3]" = "{
  54                 .com_pds_tune = 0x03,
  55                 .sq_rx_tune = 0x3,
  56                 .tx_fsls_tune = 0x3,
  57                 .tx_pre_emp_amp_tune = 0x03,
  58                 .tx_pre_emp_pulse_tune = 0x0,
  59                 .tx_rise_tune = 0x1,
  60                 .tx_vref_tune = 0x6,
  61                 .tx_hsxv_tune = 0x3,
  62                 .tx_res_tune = 0x01,
  63         }"
  64
  65         # Controller0 Port4 Default
  66         register "usb_2_port_tune_params[4]" = "{
  67                 .com_pds_tune = 0x03,
  68                 .sq_rx_tune = 0x3,
  69                 .tx_fsls_tune = 0x3,
  70                 .tx_pre_emp_amp_tune = 0x02,
  71                 .tx_pre_emp_pulse_tune = 0x0,
  72                 .tx_rise_tune = 0x1,
  73                 .tx_vref_tune = 0x5,
  74                 .tx_hsxv_tune = 0x3,
  75                 .tx_res_tune = 0x01,
  76         }"
  77
  78         # Controller0 Port5 Default
  79         register "usb_2_port_tune_params[5]" = "{
  80                 .com_pds_tune = 0x03,
  81                 .sq_rx_tune = 0x3,
  82                 .tx_fsls_tune = 0x3,
  83                 .tx_pre_emp_amp_tune = 0x02,
  84                 .tx_pre_emp_pulse_tune = 0x0,
  85                 .tx_rise_tune = 0x1,
  86                 .tx_vref_tune = 0x5,
  87                 .tx_hsxv_tune = 0x3,
  88                 .tx_res_tune = 0x01,
  89         }"
  90
  91         register "usb_pd_config_override[0]" = "{
  92                 .rfmux_override_en  = 1,
  93                 .rfmux_config = USB_PD_RFMUX_DP_X4_MODE,
  94         }"
  95         register "usb_pd_config_override[1]" = "{
  96                 .rfmux_override_en  = 1,
  97                 .rfmux_config = USB_PD_RFMUX_DP_X4_MODE,
  98         }"
  99
 100         # USB OC pin mapping; all ports share one OC pin
 101         register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
 102         register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
 103         register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
 104         register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
 105         register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
 106         register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
 107
 108         # eSPI Configuration
 109         register "common_config.espi_config" = "{
 110                 .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
 111                 .generic_io_range[0] = {
 112                         .base = 0x662,
 113                         .size = 8,
 114                 },
 115
 116                 .io_mode = ESPI_IO_MODE_SINGLE,
 117                 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 118                 .crc_check_enable = 1,
 119                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 120                 .periph_ch_en = 0,
 121                 .vw_ch_en = 0,
 122                 .oob_ch_en = 0,
 123                 .flash_ch_en = 0,
 124         }"
 125
 126         # general purpose PCIe clock output configuration
 127         register "gpp_clk_config[0]" = "GPP_CLK_OFF"
 128         register "gpp_clk_config[1]" = "GPP_CLK_OFF"
 129         register "gpp_clk_config[2]" = "GPP_CLK_REQ"
 130         register "gpp_clk_config[3]" = "GPP_CLK_ON"
 131         register "gpp_clk_config[4]" = "GPP_CLK_ON"
 132         register "gpp_clk_config[5]" = "GPP_CLK_OFF"
 133         register "gpp_clk_config[6]" = "GPP_CLK_OFF"
 134
 135         register "pspp_policy" = "DXIO_PSPP_BALANCED"
 136
 137         device domain 0 on
 138                 subsystemid 0x1022 0x1510 inherit
 139                 device ref iommu on end
 140                 device ref gpp_bridge_0 on end
 141                 device ref gpp_bridge_1 on end
 142                 device ref gpp_bridge_4 on end # NVMe
 143                 device ref internal_bridge_a on
 144                         device ref gfx on end # Internal GPU
 145                         device ref gfx_hda on end # Display HDA
 146                         device ref crypto on end # Crypto Coprocessor
 147                         device ref xhci_0 on end # USB 3.1
 148                         device ref xhci_1 off end # USB 3.1
 149                         device ref acp on end # Audio
 150                         device ref hda on end # HDA
 151                         device ref mp2 on end # non-Sensor Fusion Hub device
 152                 end
 153                 device ref internal_bridge_b on
 154                         device ref sata off end # AHCI
 155                         device ref xgbe_0 off end # integrated Ethernet MAC
 156                         device ref xgbe_1 off end # integrated Ethernet MAC
 157                 end
 158                 device ref lpc_bridge on
 159                         # chip superio/smsc/sio1036 # optional debug card
 160                 end
 161         end # domain
 162
 163         device ref uart_0 on end # console
 164         device ref uart_1 on end
 165
 166 end     # chip soc/amd/picasso