src/mainboard/amd/birman_plus/ec.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <ec/acpi/ec.h>
   5 #include <stdint.h>
   6 #include "ec.h"
   7
   8 #define BIRMAN_EC_CMD   0x666
   9 #define BIRMAN_EC_DATA  0x662
  10
  11 #define EC_GPIO_1_ADDR          0xA1
  12 #define   EC1_EVAL_PWREN        BIT(1)
  13
  14 #define EC_GPIO_2_ADDR          0xA2
  15 #define   EC2_EVAL_SLOT_PWREN   BIT(5)
  16 #define   EC2_EVAL_19V_EN       BIT(2)
  17
  18 #define EC_GPIO_3_ADDR          0xA3
  19 #define   EC3_WLAN_RST_AUX      BIT(5)
  20 #define   EC3_WWAN_RST_AUX      BIT(4)
  21 #define   EC3_SD_RST_AUX        BIT(3)
  22 #define   EC3_DT_RST_AUX        BIT(2)
  23 #define   EC3_LOM_RST_AUX       BIT(1)
  24 #define   EC3_EVAL_RST_AUX      BIT(0)
  25
  26 #define EC_GPIO_7_ADDR          0xA7
  27 #define   EC7_WWAN_PWR_OFF_N    BIT(7)
  28 #define   EC7_BT_RADIO_DIS      BIT(2)
  29 #define   EC7_WL_RADIO_DIS      BIT(0)
  30
  31 #define EC_GPIO_8_ADDR          0xA8
  32 #define   EC8_ADAPTER_OFF       BIT(5)
  33 #define   EC8_EVAL_SMBUS1_N_SW  BIT(3)
  34 #define   EC8_MP2_SEL           BIT(2)
  35 #define   EC8_DT_N_SSD1_SW      BIT(1)
  36
  37 #define EC_GPIO_9_ADDR          0xA9
  38 #define   EC9_CAM0_PWR_EN       BIT(7)
  39 #define   EC9_CAM1_PWR_EN       BIT(6)
  40 #define   EC9_WWAN_RST          BIT(5)
  41 #define   EC9_DT_PWREN          BIT(2)
  42 #define   EC9_TPM_PWR_EN        BIT(1)
  43 #define   EC9_TPM_S0I3_N        BIT(0)
  44
  45 #define EC_GPIO_A_ADDR          0xAA
  46 #define   ECA_MUX2_S0           BIT(7)
  47 #define   ECA_MUX2_S1           BIT(6)
  48 #define   ECA_MUX1_S0           BIT(5)
  49 #define   ECA_MUX1_S1           BIT(4)
  50 #define   ECA_MUX0_S0           BIT(3)
  51 #define   ECA_MUX0_S1           BIT(2)
  52 #define   ECA_SMBUS1_EN         BIT(1)
  53 #define   ECA_SMBUS0_EN         BIT(0)
  54
  55 #define EC_GPIO_C_ADDR          0xAC
  56 #define   ECC_TPNL_BUF_EN       BIT(6)
  57 #define   ECC_TPAD_BUF_EN       BIT(5)
  58 #define   ECC_NFC_BUF_EN        BIT(4)
  59
  60 #define EC_GPIO_D_ADDR          0xAD
  61 #define   ECD_TPNL_PWR_EN       BIT(7)
  62 #define   ECD_TPNL_EN           BIT(6)
  63 #define   ECD_SSD1_PWR_EN       BIT(5)
  64 #define   ECD_FPR_PWR_EN        BIT(3)
  65 #define   ECD_FPR_OFF_N         BIT(2)
  66 #define   ECD_FPR_LOCK_N        BIT(1)
  67 #define   ECD_TPAD_DISABLE_N    BIT(0)
  68
  69 #define EC_GPIO_E_ADDR          0xAE
  70 #define   ECE_LOM_PWR_EN        BIT(7)
  71 #define   ECE_SSD0_PWR_EN       BIT(6)
  72 #define   ECE_SD_PWR_EN         BIT(5)
  73 #define   ECE_WLAN_PWR_EN       BIT(4)
  74 #define   ECE_WWAN_PWR_EN       BIT(3)
  75 #define   ECE_CAM_PWR_EN        BIT(2)
  76 #define   ECE_FPR_N_GBE_SEL     BIT(1)
  77 #define   ECE_BT_N_TPNL_SEL     BIT(0)
  78
  79 #define EC_GPIO_F_ADDR          0xAF
  80 #define   ECF_CAM_FW_WP_N       BIT(7)
  81 #define   ECF_I2C_MUX_OE_N      BIT(4)
  82 #define   ECF_WLAN0_N_WWAN1_SW  BIT(1)
  83 #define   ECF_WWAN0_N_WLAN1_SW  BIT(0)
  84
  85 #define EC_GPIO_G_ADDR  0xB0
  86 #define   ECG_IR_LED_PWR_EN     BIT(7)
  87 #define   ECG_U0_WLAN_HDR_SEL   BIT(6)
  88 #define   ECG_DT_SSD1_MUX_OFF   BIT(5)
  89 #define   ECG_WLAN_WWAN_MUX_OFF BIT(4)
  90
  91 static void configure_ec_gpio(void)
  92 {
  93         uint8_t tmp;
  94
  95         tmp = ec_read(EC_GPIO_1_ADDR);
  96         if (CONFIG(ENABLE_EVAL_CARD)) {
  97                 tmp |= EC1_EVAL_PWREN;
  98         } else {
  99                 tmp &= ~EC1_EVAL_PWREN;
 100         }
 101         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_1_ADDR, tmp);
 102         ec_write(EC_GPIO_1_ADDR, tmp);
 103
 104         tmp = ec_read(EC_GPIO_2_ADDR);
 105         if (CONFIG(ENABLE_EVAL_CARD)) {
 106                 tmp |= EC2_EVAL_SLOT_PWREN;
 107                 if (CONFIG(ENABLE_EVAL_19V)) {
 108                         tmp |= EC2_EVAL_19V_EN;
 109                 } else {
 110                         tmp &= ~EC2_EVAL_19V_EN;
 111                 }
 112         } else {
 113                 tmp &= ~EC2_EVAL_SLOT_PWREN;
 114                 tmp &= ~EC2_EVAL_19V_EN;
 115         }
 116         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp);
 117         ec_write(EC_GPIO_2_ADDR, tmp);
 118
 119         tmp = ec_read(EC_GPIO_3_ADDR);
 120         tmp |= EC3_WLAN_RST_AUX | EC3_WWAN_RST_AUX | EC3_SD_RST_AUX;
 121         tmp |= EC3_DT_RST_AUX | EC3_LOM_RST_AUX | EC3_EVAL_RST_AUX;
 122         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp);
 123         ec_write(EC_GPIO_3_ADDR, tmp);
 124
 125         tmp = ec_read(EC_GPIO_7_ADDR);
 126         tmp &= ~EC7_BT_RADIO_DIS;
 127         tmp &= ~EC7_WL_RADIO_DIS;
 128         tmp |= EC7_WWAN_PWR_OFF_N;
 129         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
 130         ec_write(EC_GPIO_7_ADDR, tmp);
 131
 132         tmp = ec_read(EC_GPIO_8_ADDR);
 133         if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) {
 134                 tmp |= EC8_DT_N_SSD1_SW;
 135         } else {
 136                 tmp &= ~EC8_DT_N_SSD1_SW;
 137         }
 138         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
 139         ec_write(EC_GPIO_8_ADDR, tmp);
 140
 141         tmp = ec_read(EC_GPIO_9_ADDR);
 142         tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN;
 143         if (CONFIG(ENABLE_DT_SLOT_BIRMANPLUS)) {
 144                 tmp |= EC9_DT_PWREN;
 145         } else {
 146                 tmp &= ~EC9_DT_PWREN;
 147         }
 148         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp);
 149         ec_write(EC_GPIO_9_ADDR, tmp);
 150
 151         tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN;
 152         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_A_ADDR, tmp);
 153         ec_write(EC_GPIO_A_ADDR, tmp);
 154
 155         tmp = ec_read(EC_GPIO_C_ADDR);
 156         tmp |= ECC_TPNL_BUF_EN | ECC_TPAD_BUF_EN | ECC_NFC_BUF_EN;
 157         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_C_ADDR, tmp);
 158         ec_write(EC_GPIO_C_ADDR, tmp);
 159
 160         tmp = ec_read(EC_GPIO_D_ADDR);
 161         tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N;
 162         if (CONFIG(ENABLE_M2_SSD1_BIRMANPLUS)) {
 163                 tmp |= ECD_SSD1_PWR_EN;
 164         } else {
 165                 tmp &= ~ECD_SSD1_PWR_EN;
 166         }
 167         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp);
 168         ec_write(EC_GPIO_D_ADDR, tmp);
 169
 170         tmp = ec_read(EC_GPIO_E_ADDR);
 171         tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN;
 172         tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL;
 173         tmp &= ~ECE_BT_N_TPNL_SEL;
 174         if (CONFIG(WLAN01_BIRMANPLUS)) {        // no WWAN, turn off WWAN power
 175                 tmp &= ~ECE_WWAN_PWR_EN;
 176         } else {
 177                 tmp |= ECE_WWAN_PWR_EN;
 178         }
 179         if (CONFIG(WWAN01_BIRMANPLUS)) {        // no WLAN, turn off WLAN power
 180                 tmp &= ~ECE_WLAN_PWR_EN;
 181         } else {
 182                 tmp |= ECE_WLAN_PWR_EN;
 183         }
 184         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_E_ADDR, tmp);
 185         ec_write(EC_GPIO_E_ADDR, tmp);
 186
 187         tmp = ec_read(EC_GPIO_F_ADDR);
 188         if (CONFIG(WLAN01_BIRMANPLUS)) {
 189                 tmp |= ECF_WWAN0_N_WLAN1_SW;
 190         } else {
 191                 tmp &= ~ECF_WWAN0_N_WLAN1_SW;
 192         }
 193         if (CONFIG(WWAN01_BIRMANPLUS)) {
 194                 tmp |= ECF_WLAN0_N_WWAN1_SW;
 195         } else {
 196                 tmp &= ~ECF_WLAN0_N_WWAN1_SW;
 197         }
 198         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_F_ADDR, tmp);
 199         ec_write(EC_GPIO_F_ADDR, tmp);
 200
 201         tmp = ec_read(EC_GPIO_G_ADDR);
 202         tmp &= ~ECG_DT_SSD1_MUX_OFF;
 203         tmp &= ~ECG_WLAN_WWAN_MUX_OFF;
 204         tmp |= ECG_IR_LED_PWR_EN | ECG_U0_WLAN_HDR_SEL;
 205         printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_G_ADDR, tmp);
 206         ec_write(EC_GPIO_G_ADDR, tmp);
 207 }
 208
 209 void birman_ec_init(void)
 210 {
 211         ec_set_ports(BIRMAN_EC_CMD, BIRMAN_EC_DATA);
 212         configure_ec_gpio();
 213 }