src/mainboard/amd/gardenia/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <gpio.h>
   4 #include <soc/southbridge.h>
   5
   6 #include "gpio.h"
   7
   8 /*
   9  * As a rule of thumb, GPIO pins used by coreboot should be initialized at
  10  * bootblock while GPIO pins used only by the OS should be initialized at
  11  * ramstage.
  12  */
  13 static const struct soc_amd_gpio gpio_set_stage_reset[] = {
  14         /* NFC PU */
  15         PAD_GPO(GPIO_64, HIGH),
  16         /* PCIe presence detect */
  17         PAD_GPI(GPIO_69, PULL_UP),
  18         /* MUX for Power Express Eval */
  19         PAD_GPI(GPIO_116, PULL_DOWN),
  20         /* SD power */
  21         PAD_GPO(GPIO_119, HIGH),
  22         /* GPIO_136 - UART0_FCH_RX_DEBUG_RX */
  23         PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
  24         /* GPIO_137 - UART0_FCH_DEBUG_RTS */
  25         PAD_NF(GPIO_137, UART0_RTS_L, PULL_NONE),
  26         /* GPIO_138 - UART0_FCH_TX_DEBUG_RX */
  27         PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
  28         /* GPIO_142 - UART1_FCH_RTS */
  29         PAD_NF(GPIO_142, UART1_RTS_L, PULL_NONE),
  30         /* GPIO_143 - UART1_FCH_TX */
  31         PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
  32 };
  33
  34 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
  35         /* BT radio disable */
  36         PAD_GPO(GPIO_14, HIGH),
  37         /* NFC wake */
  38         PAD_GPO(GPIO_65, HIGH),
  39         /* Webcam */
  40         PAD_GPO(GPIO_66, HIGH),
  41         /* GPS sleep */
  42         PAD_GPO(GPIO_70, HIGH),
  43 };
  44
  45 const struct soc_amd_gpio *early_gpio_table(size_t *size)
  46 {
  47         *size = ARRAY_SIZE(gpio_set_stage_reset);
  48         return gpio_set_stage_reset;
  49 }
  50
  51 const struct soc_amd_gpio *gpio_table(size_t *size)
  52 {
  53         *size = ARRAY_SIZE(gpio_set_stage_ram);
  54         return gpio_set_stage_ram;
  55 }