1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* DefinitionBlock Statement */
11 0x00010001 /* OEM Revision */
13 { /* Start of ASL file */
14 #include <acpi/dsdt_top.asl>
15 #include <globalnvs.asl>
17 /* Describe the USB Overcurrent pins */
18 #include "acpi/usb_oc.asl"
20 /* PCI IRQ mapping for the Southbridge */
23 /* Power state notification */
26 /* Contains the supported sleep states for this chipset */
27 #include <soc/amd/common/acpi/sleepstates.asl>
29 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
30 #include "acpi/sleep.asl"
33 Scope(\_SB) { /* Start \_SB scope */
34 /* global utility methods expected within the \_SB scope */
35 #include <arch/x86/acpi/globutil.asl>
37 /* IRQ Routing mapping for this platform (in \_SB scope) */
38 #include "acpi/routing.asl"
41 Name(_HID, EISAID("PNP0C0C"))
43 Name(_PRW, Package () {3, 0x04})
47 /* Describe the SOC */
50 /* Describe the Fintek F81803A SIO */
51 #define SUPERIO_DEV SIO0
52 #define SUPERIO_PNP_BASE 0x4E
53 #define F81803A_SHOW_UARTA
54 #define F81803A_SHOW_PME
55 #include <superio/fintek/f81803a/acpi/superio.asl>
57 } /* End \_SB scope */
59 /* Define the General Purpose Events for the platform */
60 #include "acpi/gpe.asl"