src/mainboard/amd/pademelon/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <device/device.h>
   5 #include <amdblocks/agesawrapper.h>
   6 #include <amdblocks/amd_pci_util.h>
   7 #include <gpio.h>
   8 #include <soc/acpi.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/southbridge.h>
  11
  12 #include "gpio.h"
  13
  14 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  15    accessed via I/O ports 0xc00/0xc01. */
  16 static const struct fch_irq_routing fch_irq_map[] = {
  17         { PIRQ_A,        3,             16 },
  18         { PIRQ_B,        4,             17 },
  19         { PIRQ_C,        5,             18 },
  20         { PIRQ_D,        7,             19 },
  21         { PIRQ_E,       11,             20 },
  22         { PIRQ_F,       10,             21 },
  23         { PIRQ_G,       PIRQ_NC,        22 },
  24         { PIRQ_H,       PIRQ_NC,        23 },
  25         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  26         { PIRQ_SMBUS,   PIRQ_NC,        PIRQ_NC },
  27         { PIRQ_HDA,      3,             16 },
  28         { PIRQ_SD,      PIRQ_NC,        16 },
  29         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  30         { PIRQ_EHCI,     5,             18 },
  31         { PIRQ_XHCI,     4,             18 },
  32         { PIRQ_SATA,    PIRQ_NC,        19 },
  33         { PIRQ_GPIO,     7,              7 },
  34         { PIRQ_I2C0,     3,              3 },
  35         { PIRQ_I2C1,    15,             15 },
  36         { PIRQ_I2C2,     6,              6 },
  37         { PIRQ_I2C3,    14,             14 },
  38         { PIRQ_UART0,   10,             10 },
  39         { PIRQ_UART1,   11,             11 },
  40
  41         /* The MISC registers are not interrupt numbers */
  42         { PIRQ_MISC,    0xfa,   0x00 },
  43         { PIRQ_MISC0,   0xf1,   0x00 },
  44         { PIRQ_MISC1,   0x00,   0x00 },
  45         { PIRQ_MISC2,   0x00,   0x00 },
  46 };
  47
  48 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  49 {
  50         *length = ARRAY_SIZE(fch_irq_map);
  51         return fch_irq_map;
  52 }
  53
  54 /*
  55  * This table defines the index into the picr/intr_data tables for each
  56  * device.  Any enabled device and slot that uses hardware interrupts should
  57  * have an entry in this table to define its index into the FCH PCI_INTR
  58  * register 0xC00/0xC01.  This index will define the interrupt that it should
  59  *  use. Putting PIRQ_A into the PIN A index for a device will tell that
  60  * device to use PIC IRQ 10 if it uses PIN A for its hardware INT.
  61  */
  62 static const struct pirq_struct mainboard_pirq_data[] = {
  63         { GFX_DEVFN,    { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  64         { HDA0_DEVFN,   { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } },
  65         { PCIE0_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  66         { PCIE1_DEVFN,  { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } },
  67         { PCIE2_DEVFN,  { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } },
  68         { PCIE3_DEVFN,  { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } },
  69         { PCIE4_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  70         { PSP_DEVFN,    { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  71         { HDA1_DEVFN,   { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  72         { SD_DEVFN,     { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  73         { SMBUS_DEVFN,  { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  74         { SATA_DEVFN,   { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  75         { EHCI1_DEVFN,  { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  76         { XHCI_DEVFN,   { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  77 };
  78
  79 /* PIRQ Setup */
  80 static void pirq_setup(void)
  81 {
  82         pirq_data_ptr = mainboard_pirq_data;
  83         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
  84 }
  85
  86 static void mainboard_init(void *chip_info)
  87 {
  88         size_t num_gpios;
  89         const struct soc_amd_gpio *gpios;
  90         gpios = gpio_table(&num_gpios);
  91         gpio_configure_pads(gpios, num_gpios);
  92 }
  93
  94 /*************************************************
  95  * enable the dedicated function in pademelon board.
  96  *************************************************/
  97 static void mainboard_enable(struct device *dev)
  98 {
  99         /* Initialize the PIRQ data structures for consumption */
 100         pirq_setup();
 101 }
 102
 103 struct chip_operations mainboard_ops = {
 104         .init = mainboard_init,
 105         .enable_dev = mainboard_enable,
 106 };