src/mainboard/asrock/h77pro4-m/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <bootblock_common.h>
   5 #include <device/pci_ops.h>
   6 #include <device/pnp_ops.h>
   7 #include <option.h>
   8 #include <southbridge/intel/bd82x6x/pch.h>
   9 #include <superio/nuvoton/common/nuvoton.h>
  10 #include <superio/nuvoton/nct6776/nct6776.h>
  11
  12 #define GLOBAL_DEV   PNP_DEV(0x2e, 0)
  13 #define SERIAL_DEV   PNP_DEV(0x2e, NCT6776_SP1)
  14 #define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V)
  15
  16 /* As defined in cmos.layout */
  17 enum cpu_fan_tach_src {
  18         CPU_FAN_HEADER_NONE,
  19         CPU_FAN_HEADER_1,
  20         CPU_FAN_HEADER_2,
  21         CPU_FAN_HEADER_BOTH
  22 };
  23
  24 const struct southbridge_usb_port mainboard_usb_ports[] = {
  25         { 1, 0, 0 },
  26         { 1, 0, 0 },
  27         { 1, 1, 1 },
  28         { 1, 1, 1 },
  29         { 1, 1, 2 },
  30         { 1, 1, 2 },
  31         { 1, 0, 3 },
  32         { 1, 0, 3 },
  33         { 1, 0, 4 },
  34         { 1, 0, 4 },
  35         { 1, 0, 6 },
  36         { 1, 1, 5 },
  37         { 1, 1, 5 },
  38         { 1, 0, 6 },
  39 };
  40
  41 /*
  42  * The tachometer signal that goes to CPUFANIN of the Super I/O is set via
  43  * GPIOs.
  44  *
  45  * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected.
  46  * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected.
  47  * When both are '0' and both fans are connected, wrong readings will
  48  * be reported.
  49  */
  50 static u8 get_cpufanin_gpio_config(void)
  51 {
  52         switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) {
  53         case CPU_FAN_HEADER_NONE:
  54                 return 0xff;
  55         case CPU_FAN_HEADER_1:
  56         default:
  57                 return 0x7f;
  58         case CPU_FAN_HEADER_2:
  59                 return 0xbf;
  60         case CPU_FAN_HEADER_BOTH:
  61                 return 0x3f;
  62         }
  63 };
  64
  65 void bootblock_mainboard_early_init(void)
  66 {
  67         nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
  68
  69         /* Configure Super I/O pins */
  70         pnp_write_config(GLOBAL_DEV, 0x1b, 0x68);
  71         pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
  72         pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
  73         pnp_write_config(GLOBAL_DEV, 0x27, 0xc0);
  74         pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
  75         pnp_write_config(GLOBAL_DEV, 0x2b, 0x08);
  76         pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
  77
  78         /* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */
  79         pnp_set_logical_device(GPIO6789_DEV);
  80         pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f);
  81         pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config());
  82
  83         nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
  84
  85         /* Enable UART */
  86         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  87 }