| blob | d65f2de0ec068aa8f4fe12482ddca5c38fde75be |
1 /* Bochs/QEMU ACPI DSDT ASL definition */
2 /* SPDX-License-Identifier: GPL-2.0-only */
4 /*
5 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
6 */
8 #include <acpi/acpi.h>
9 DefinitionBlock (
10 "dsdt.aml",
11 "DSDT",
12 ACPI_DSDT_REV_1,
13 OEM_ID,
14 ACPI_TABLE_CREATOR,
15 0x2 // OEM Revision
16 )
17 {
18 #include <acpi/dsdt_top.asl>
20 #include "../qemu-i440fx/acpi/dbug.asl"
22 Scope(\_SB) {
23 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
24 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
25 Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
26 PCIB, 8,
27 }
28 }
31 /****************************************************************
32 * PCI Bus definition
33 ****************************************************************/
35 Scope(\_SB) {
36 Device(PCI0) {
37 Name(_HID, EisaId("PNP0A08"))
38 Name(_CID, EisaId("PNP0A03"))
39 Name(_UID, 1)
41 // _OSC: based on sample of ACPI3.0b spec
42 Name(SUPP, 0) // PCI _OSC Support Field value
43 Name(CTRL, 0) // PCI _OSC Control Field value
44 Method(_OSC, 4) {
45 // Create DWORD-addressable fields from the Capabilities Buffer
46 CreateDWordField(Arg3, 0, CDW1)
48 // Check for proper UUID
49 If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
50 // Create DWORD-addressable fields from the Capabilities Buffer
51 CreateDWordField(Arg3, 4, CDW2)
52 CreateDWordField(Arg3, 8, CDW3)
54 // Save Capabilities DWORD2 & 3
55 SUPP = CDW2
56 CTRL = CDW3
58 // Always allow native PME, AER (no dependencies)
59 // Never allow SHPC (no SHPC controller in this system)
60 CTRL &= 0x1D
62 If (Arg1 != 1) {
63 // Unknown revision
64 CDW1 |= 0x08
65 }
66 If (CDW3 != CTRL) {
67 // Capabilities bits were masked
68 CDW1 |= 0x10
69 }
70 // Update DWORD3 in the buffer
71 CDW3 = CTRL
72 } Else {
73 CDW1 |= 4 // Unrecognized UUID
74 }
75 Return (Arg3)
76 }
77 }
78 }
80 #include "../qemu-i440fx/acpi/pci-crs.asl"
81 #include "../qemu-i440fx/acpi/hpet.asl"
84 /****************************************************************
85 * VGA
86 ****************************************************************/
88 Scope(\_SB.PCI0) {
89 Device(VGA) {
90 Name(_ADR, 0x00010000)
91 Method(_S1D, 0, NotSerialized) {
92 Return (0x00)
93 }
94 Method(_S2D, 0, NotSerialized) {
95 Return (0x00)
96 }
97 Method(_S3D, 0, NotSerialized) {
98 Return (0x00)
99 }
100 }
101 }
104 /****************************************************************
105 * LPC ISA bridge
106 ****************************************************************/
108 Scope(\_SB.PCI0) {
109 /* PCI D31:f0 LPC ISA bridge */
110 Device(ISA) {
111 /* PCI D31:f0 */
112 Name(_ADR, 0x001f0000)
114 /* ICH9 PCI to ISA irq remapping */
115 OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
117 OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
118 Field(LPCD, AnyAcc, NoLock, Preserve) {
119 COMA, 3,
120 , 1,
121 COMB, 3,
123 Offset(0x01),
124 LPTD, 2,
125 , 2,
126 FDCD, 2
127 }
128 OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
129 Field(LPCE, AnyAcc, NoLock, Preserve) {
130 CAEN, 1,
131 CBEN, 1,
132 LPEN, 1,
133 FDEN, 1
134 }
135 }
136 }
138 #include "../qemu-i440fx/acpi/isa.asl"
141 /****************************************************************
142 * PCI IRQs
143 ****************************************************************/
145 Scope(\_SB) {
146 Scope(PCI0) {
147 #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
148 Package() { nr##ffff, 0, lnk0, 0 }, \
149 Package() { nr##ffff, 1, lnk1, 0 }, \
150 Package() { nr##ffff, 2, lnk2, 0 }, \
151 Package() { nr##ffff, 3, lnk3, 0 }
153 #define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
154 #define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
155 #define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
156 #define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
158 #define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
159 #define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
160 #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
161 #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
163 Name(PRTP, Package() {
164 prt_slot_lnkE(0x0000),
165 prt_slot_lnkF(0x0001),
166 prt_slot_lnkG(0x0002),
167 prt_slot_lnkH(0x0003),
168 prt_slot_lnkE(0x0004),
169 prt_slot_lnkF(0x0005),
170 prt_slot_lnkG(0x0006),
171 prt_slot_lnkH(0x0007),
172 prt_slot_lnkE(0x0008),
173 prt_slot_lnkF(0x0009),
174 prt_slot_lnkG(0x000a),
175 prt_slot_lnkH(0x000b),
176 prt_slot_lnkE(0x000c),
177 prt_slot_lnkF(0x000d),
178 prt_slot_lnkG(0x000e),
179 prt_slot_lnkH(0x000f),
180 prt_slot_lnkE(0x0010),
181 prt_slot_lnkF(0x0011),
182 prt_slot_lnkG(0x0012),
183 prt_slot_lnkH(0x0013),
184 prt_slot_lnkE(0x0014),
185 prt_slot_lnkF(0x0015),
186 prt_slot_lnkG(0x0016),
187 prt_slot_lnkH(0x0017),
188 prt_slot_lnkE(0x0018),
190 /* INTA -> PIRQA for slot 25 - 31
191 see the default value of D<N>IR */
192 prt_slot_lnkA(0x0019),
193 prt_slot_lnkA(0x001a),
194 prt_slot_lnkA(0x001b),
195 prt_slot_lnkA(0x001c),
196 prt_slot_lnkA(0x001d),
198 /* PCIe->PCI bridge. use PIRQ[E-H] */
199 prt_slot_lnkE(0x001e),
201 prt_slot_lnkA(0x001f)
202 })
204 #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
205 Package() { nr##ffff, 0, gsi0, 0 }, \
206 Package() { nr##ffff, 1, gsi1, 0 }, \
207 Package() { nr##ffff, 2, gsi2, 0 }, \
208 Package() { nr##ffff, 3, gsi3, 0 }
210 #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
211 #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
212 #define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
213 #define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
215 #define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
216 #define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
217 #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
218 #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
220 Name(PRTA, Package() {
221 prt_slot_gsiE(0x0000),
222 prt_slot_gsiF(0x0001),
223 prt_slot_gsiG(0x0002),
224 prt_slot_gsiH(0x0003),
225 prt_slot_gsiE(0x0004),
226 prt_slot_gsiF(0x0005),
227 prt_slot_gsiG(0x0006),
228 prt_slot_gsiH(0x0007),
229 prt_slot_gsiE(0x0008),
230 prt_slot_gsiF(0x0009),
231 prt_slot_gsiG(0x000a),
232 prt_slot_gsiH(0x000b),
233 prt_slot_gsiE(0x000c),
234 prt_slot_gsiF(0x000d),
235 prt_slot_gsiG(0x000e),
236 prt_slot_gsiH(0x000f),
237 prt_slot_gsiE(0x0010),
238 prt_slot_gsiF(0x0011),
239 prt_slot_gsiG(0x0012),
240 prt_slot_gsiH(0x0013),
241 prt_slot_gsiE(0x0014),
242 prt_slot_gsiF(0x0015),
243 prt_slot_gsiG(0x0016),
244 prt_slot_gsiH(0x0017),
245 prt_slot_gsiE(0x0018),
247 /* INTA -> PIRQA for slot 25 - 31, but 30
248 see the default value of D<N>IR */
249 prt_slot_gsiA(0x0019),
250 prt_slot_gsiA(0x001a),
251 prt_slot_gsiA(0x001b),
252 prt_slot_gsiA(0x001c),
253 prt_slot_gsiA(0x001d),
255 /* PCIe->PCI bridge. use PIRQ[E-H] */
256 prt_slot_gsiE(0x001e),
258 prt_slot_gsiA(0x001f)
259 })
261 Method(_PRT, 0, NotSerialized) {
262 /* PCI IRQ routing table, example from ACPI 2.0a specification,
263 section 6.2.8.1 */
264 /* Note: we provide the same info as the PCI routing
265 table of the Bochs BIOS */
266 If (\PICM == 0) {
267 Return (PRTP)
268 } Else {
269 Return (PRTA)
270 }
271 }
272 }
274 Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
275 PRQA, 8,
276 PRQB, 8,
277 PRQC, 8,
278 PRQD, 8,
280 Offset(0x08),
281 PRQE, 8,
282 PRQF, 8,
283 PRQG, 8,
284 PRQH, 8
285 }
287 Method(IQST, 1, NotSerialized) {
288 // _STA method - get status
289 If (0x80 & Arg0) {
290 Return (0x09)
291 }
292 Return (0x0B)
293 }
294 Method(IQCR, 1, Serialized) {
295 // _CRS method - get current settings
296 Name(PRR0, ResourceTemplate() {
297 Interrupt(, Level, ActiveHigh, Shared) { 0 }
298 })
299 CreateDWordField(PRR0, 0x05, PRRI)
300 PRRI = Arg0 & 0x0F
301 Return (PRR0)
302 }
304 #define define_link(link, uid, reg) \
305 Device(link) { \
306 Name(_HID, EISAID("PNP0C0F")) \
307 Name(_UID, uid) \
308 Name(_PRS, ResourceTemplate() { \
309 Interrupt(, Level, ActiveHigh, Shared) { \
310 5, 10, 11 \
311 } \
312 }) \
313 Method(_STA, 0, NotSerialized) { \
314 Return (IQST(reg)) \
315 } \
316 Method(_DIS, 0, NotSerialized) { \
317 reg |= 0x80 \
318 } \
319 Method(_CRS, 0, NotSerialized) { \
320 Return (IQCR(reg)) \
321 } \
322 Method(_SRS, 1, NotSerialized) { \
323 CreateDWordField(Arg0, 0x05, PRRI) \
324 reg = PRRI \
325 } \
326 }
328 define_link(LNKA, 0, PRQA)
329 define_link(LNKB, 1, PRQB)
330 define_link(LNKC, 2, PRQC)
331 define_link(LNKD, 3, PRQD)
332 define_link(LNKE, 4, PRQE)
333 define_link(LNKF, 5, PRQF)
334 define_link(LNKG, 6, PRQG)
335 define_link(LNKH, 7, PRQH)
337 #define define_gsi_link(link, uid, gsi) \
338 Device(link) { \
339 Name(_HID, EISAID("PNP0C0F")) \
340 Name(_UID, uid) \
341 Name(_PRS, ResourceTemplate() { \
342 Interrupt(, Level, ActiveHigh, Shared) { \
343 gsi \
344 } \
345 }) \
346 Name(_CRS, ResourceTemplate() { \
347 Interrupt(, Level, ActiveHigh, Shared) { \
348 gsi \
349 } \
350 }) \
351 Method(_SRS, 1, NotSerialized) { \
352 } \
353 }
355 define_gsi_link(GSIA, 0, 0x10)
356 define_gsi_link(GSIB, 0, 0x11)
357 define_gsi_link(GSIC, 0, 0x12)
358 define_gsi_link(GSID, 0, 0x13)
359 define_gsi_link(GSIE, 0, 0x14)
360 define_gsi_link(GSIF, 0, 0x15)
361 define_gsi_link(GSIG, 0, 0x16)
362 define_gsi_link(GSIH, 0, 0x17)
363 }
365 /****************************************************************
366 * General purpose events
367 ****************************************************************/
369 Scope(\_GPE) {
370 Name(_HID, "ACPI0006")
372 Method(_L00) {
373 }
374 Method(_L01) {
375 }
376 Method(_L02) {
377 }
378 Method(_L03) {
379 }
380 Method(_L04) {
381 }
382 Method(_L05) {
383 }
384 Method(_L06) {
385 }
386 Method(_L07) {
387 }
388 Method(_L08) {
389 }
390 Method(_L09) {
391 }
392 Method(_L0A) {
393 }
394 Method(_L0B) {
395 }
396 Method(_L0C) {
397 }
398 Method(_L0D) {
399 }
400 Method(_L0E) {
401 }
402 Method(_L0F) {
403 }
404 }
405 }