src/mainboard/hp/280_g2/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <console/console.h>
   5 #include <device/pnp_ops.h>
   6 #include <gpio.h>
   7 #include <superio/ite/common/ite.h>
   8 #include <types.h>
   9
  10 static const struct pad_config gpio_table[] = {
  11         PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),                       /* SPKR */
  12         PAD_CFG_NF(GPP_C20, UP_20K, PLTRST, NF1),                       /* PCH_UART2_RXD */
  13         PAD_CFG_NF(GPP_C21, UP_20K, PLTRST, NF1),                       /* PCH_UART2_TXD */
  14         PAD_NC(GPP_C22, NONE),
  15         PAD_CFG_GPI(GPP_C23, NONE, PLTRST),                             /* TODO: SIO PME# */
  16         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),                            /* SATA_LED# */
  17         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),                            /* USB_OC_LAN# */
  18         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),                           /* USB3.0_OC_BACK# */
  19         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),                           /* USB_OC_REAR2# */
  20         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),                           /* USB_OC_FRONT1# */
  21         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),                           /* USB_OC_FRONT2# */
  22         PAD_CFG_GPI(GPP_G1, NONE, PLTRST),                              /* LPT_DET# */
  23         PAD_CFG_GPO(GPP_G2, 0, PLTRST),                                 /* AUD_AMP_ON# */
  24         PAD_CFG_GPO(GPP_G3, 0, PLTRST),                                 /* W_DISABLE2# */
  25         PAD_CFG_GPI(GPP_G4, NONE, PLTRST),                              /* CLR_CMOS# */
  26         PAD_CFG_GPI(GPP_G5, NONE, PLTRST),                              /* CLR_PSWD# */
  27         PAD_CFG_GPI(GPP_G6, NONE, PLTRST),                              /* BOOT_BLOCK_EN# */
  28         PAD_CFG_GPI(GPP_G9, NONE, PLTRST),                              /* HOOD_SW_DET# */
  29         PAD_CFG_GPI(GPP_G12, NONE, PLTRST),                             /* FRONT_USB_DET1# */
  30         PAD_CFG_GPI(GPP_G13, NONE, PLTRST),                             /* FRONT_USB_DET2# */
  31         PAD_CFG_GPI(GPP_G14, NONE, PLTRST),                             /* FRONT_USB_DET3# */
  32         PAD_CFG_GPI(GPP_G16, NONE, PLTRST),                             /* F_AUDIO_DET# */
  33         PAD_CFG_GPI(GPP_G17, NONE, PLTRST),                             /* COMM_B_DET# */
  34         PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT),      /* SPI_TPM_PIRQ# */
  35         PAD_CFG_GPI(GPP_H10, NONE, PLTRST),                             /* S_GPI_SKU0 */
  36         PAD_CFG_GPI(GPP_H15, NONE, PLTRST),                             /* BRD_REV0 */
  37         PAD_CFG_GPI(GPP_H16, NONE, PLTRST),                             /* BRD_REV1 */
  38         PAD_CFG_GPI(GPP_H17, NONE, PLTRST),                             /* BRD_REV2 */
  39         PAD_CFG_GPI(GPP_H18, NONE, PLTRST),                             /* S_GPI_SKU1 */
  40         PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),                          /* DPD_HPD_R */
  41         PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),                          /* DPE_HPD_R */
  42         PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1),                          /* DDPD_CTRLCLK */
  43         PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1),                       /* DDPD_CTRLDATA */
  44 };
  45
  46 static void mainboard_configure_super_io(void)
  47 {
  48         const pnp_devfn_t dev = PNP_DEV(0x2e, 7);
  49
  50         pnp_enter_conf_state(dev);
  51         pnp_set_logical_device(dev);
  52
  53         pnp_write_config(dev, 0x23, 0x59);
  54         pnp_write_config(dev, 0x25, 0x10);
  55         pnp_write_config(dev, 0x26, 0x04);
  56         pnp_write_config(dev, 0x28, 0x08);
  57         pnp_write_config(dev, 0x2a, 0x81);
  58         pnp_write_config(dev, 0x71, 0x08);
  59         pnp_write_config(dev, 0xc0, 0x00);
  60         pnp_write_config(dev, 0xc1, 0x04);
  61         pnp_write_config(dev, 0xc8, 0x00);
  62         pnp_write_config(dev, 0xc9, 0x04);
  63         pnp_write_config(dev, 0xcb, 0x08);
  64         pnp_write_config(dev, 0xd5, 0x07);
  65         pnp_write_config(dev, 0xf8, 0x12);
  66         pnp_write_config(dev, 0xf9, 0x01);
  67
  68         pnp_exit_conf_state(dev);
  69 }
  70
  71 void bootblock_mainboard_early_init(void)
  72 {
  73         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
  74
  75         mainboard_configure_super_io();
  76 }
  77
  78 void bootblock_mainboard_init(void)
  79 {
  80         const gpio_t rev_gpios[] = {
  81                 GPP_H15,
  82                 GPP_H16,
  83                 GPP_H17,
  84         };
  85
  86         const char *const rev_table[8] = {
  87                 [0] = "DB",
  88                 [1] = "Pre-SI",
  89                 [2] = "SI",
  90                 [3] = "PV",
  91                 [4] = "1.00 (SMVB)",
  92                 [5] = "1.10 (ECN1)",
  93                 [6] = "1.20 (ECN1)",
  94                 [7] = "1.30 (ECN1)",
  95         };
  96
  97         const char *const brd_str = gpio_get(GPP_H10) ? "Sid" : "Manny";
  98
  99         const uint32_t brd_rev = gpio_base2_value(rev_gpios, ARRAY_SIZE(rev_gpios));
 100
 101         printk(BIOS_DEBUG, "Mainboard: %s rev %s\n", brd_str, rev_table[brd_rev]);
 102 }