src/mainboard/intel/harcuvar/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _MAINBOARD_GPIO_H
   4 #define _MAINBOARD_GPIO_H
   5
   6 #include <soc/gpio_dnv.h>
   7
   8 #ifndef __ACPI__
   9 const struct dnv_pad_config harcuvar_gpio_table[] = {
  10         // GBE0_SDP0 (GPIO_14)
  11         {NORTH_ALL_GBE0_SDP0,
  12          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  13           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  14         // GBE1_SDP0 (GPIO_15)
  15         {NORTH_ALL_GBE1_SDP0,
  16          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  17           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  18         // GBE2_I2C_CLK (GPIO_16)
  19         {NORTH_ALL_GBE0_SDP1,
  20          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  21           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  22         // GBE2_I2C_DATA (GPIO_17)
  23         {NORTH_ALL_GBE1_SDP1,
  24          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  25           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  26         // GBE2_SDP0 (GPIO_18)
  27         {NORTH_ALL_GBE0_SDP2,
  28          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  29           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  30         // GBE3_SDP0 (GPIO_19)
  31         {NORTH_ALL_GBE1_SDP2,
  32          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  33           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  34         // GBE3_I2C_CLK (GPIO_20)
  35         {NORTH_ALL_GBE0_SDP3,
  36          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  37           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  38         // GBE3_I2C_DATA (GPIO_21)
  39         {NORTH_ALL_GBE1_SDP3,
  40          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  41           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  42         // GBE2_LED0 (GPIO_22)
  43         {NORTH_ALL_GBE2_LED0,
  44          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  45           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  46         // GBE2_LED1 (GPIO_23)
  47         {NORTH_ALL_GBE2_LED1,
  48          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  49           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  50         // GBE0_I2C_CLK (GPIO_24)
  51         {NORTH_ALL_GBE0_I2C_CLK,
  52          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  53           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  54         // GBE0_I2C_DATA (GPIO_25)
  55         {NORTH_ALL_GBE0_I2C_DATA,
  56          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  57           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  58         // GBE1_I2C_CLK (GPIO_26)
  59         {NORTH_ALL_GBE1_I2C_CLK,
  60          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  61           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  62         // GBE1_I2C_DATA (GPIO_27)
  63         {NORTH_ALL_GBE1_I2C_DATA,
  64          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
  65           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
  66         // NCSI_RXD0 (GPIO_28)
  67         {NORTH_ALL_NCSI_RXD0,
  68          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  69           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  70         // NCSI_CLK_IN (GPIO_29)
  71         {NORTH_ALL_NCSI_CLK_IN,
  72          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  73           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  74         // NCSI_RXD1 (GPIO_30)
  75         {NORTH_ALL_NCSI_RXD1,
  76          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  77           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  78         // NCSI_CRS_DV (GPIO_31)
  79         {NORTH_ALL_NCSI_CRS_DV,
  80          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  81           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  82         // NCSI_ARB_IN (GPIO_32)
  83         {NORTH_ALL_NCSI_ARB_IN,
  84          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  85           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  86         // NCSI_TX_EN (GPIO_33)
  87         {NORTH_ALL_NCSI_TX_EN,
  88          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
  89           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  90         // NCSI_TXD0 (GPIO_34)
  91         {NORTH_ALL_NCSI_TXD0,
  92          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  93           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  94         // NCSI_TXD1 (GPIO_35)
  95         {NORTH_ALL_NCSI_TXD1,
  96          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
  97           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
  98         // NCSI_ARB_OUT (GPIO_36)
  99         {NORTH_ALL_NCSI_ARB_OUT,
 100          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 101           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 102         // GBE0_LED0 (GPIO_37)
 103         {NORTH_ALL_GBE0_LED0,
 104          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 105           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 106         // GBE0_LED1 (GPIO_38)
 107         {NORTH_ALL_GBE0_LED1,
 108          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 109           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 110         // GBE1_LED0 (GPIO_39)
 111         {NORTH_ALL_GBE1_LED0,
 112          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 113           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 114         // GBE1_LED1 (GPIO_40)
 115         {NORTH_ALL_GBE1_LED1,
 116          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 117           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 118         // ADR-COMPLETE (GPIO_0)
 119         {NORTH_ALL_GPIO_0,
 120          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 121           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 122         // PCIE_CLKREQ0_N (GPIO_41)
 123         {NORTH_ALL_PCIE_CLKREQ0_N,
 124          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 125           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 126         // PCIE_CLKREQ1_N (GPIO_42)
 127         {NORTH_ALL_PCIE_CLKREQ1_N,
 128          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 129           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 130         // PCIE_CLKREQ2_N (GPIO_43)
 131         {NORTH_ALL_PCIE_CLKREQ2_N,
 132          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 133           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 134         // PCIE_CLKREQ3_N (GPIO_44)
 135         {NORTH_ALL_PCIE_CLKREQ3_N,
 136          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 137           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 138         // FORCE_POWER (GPIO_45)
 139         {NORTH_ALL_PCIE_CLKREQ4_N,
 140          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 141           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 142         // GBE_MDC (GPIO_1)
 143         {NORTH_ALL_GPIO_1,
 144          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 145           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 146         // GBE_MDIO  (GPIO_2)
 147         {NORTH_ALL_GPIO_2,
 148          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 149           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 150         // SVID_ALERT_N (GPIO_47)
 151         {NORTH_ALL_SVID_ALERT_N,
 152          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 153           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 154         // SVID_DATA (GPIO_48)
 155         {NORTH_ALL_SVID_DATA,
 156          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 157           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 158         // SVID_CLK (GPIO_49)
 159         {NORTH_ALL_SVID_CLK,
 160          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 161           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 162         // THERMTRIP_N (GPIO_50)
 163         {NORTH_ALL_THERMTRIP_N,
 164          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 165           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 166         // PROCHOT_N (GPIO_51)
 167         {NORTH_ALL_PROCHOT_N,
 168          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 169           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 170         // MEMHOT_N (GPIO_52)
 171         {NORTH_ALL_MEMHOT_N,
 172          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 173           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 174         // DFX_PORT_CLK0 (GPIO_53)
 175         {SOUTH_DFX_DFX_PORT_CLK0,
 176          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 177           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 178         // DFX_PORT_CLK1 (GPIO_54)
 179         {SOUTH_DFX_DFX_PORT_CLK1,
 180          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 181           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 182         // DFX_PORT0 (GPIO_55)
 183         {SOUTH_DFX_DFX_PORT0,
 184          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 185           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 186         // DFX_PORT1 (GPIO_56)
 187         {SOUTH_DFX_DFX_PORT1,
 188          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 189           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 190         // DFX_PORT2 (GPIO_57)
 191         {SOUTH_DFX_DFX_PORT2,
 192          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 193           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 194         // DFX_PORT3 (GPIO_58)
 195         {SOUTH_DFX_DFX_PORT3,
 196          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 197           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 198         // DFX_PORT4 (GPIO_59)
 199         {SOUTH_DFX_DFX_PORT4,
 200          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 201           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 202         // DFX_PORT5 (GPIO_60)
 203         {SOUTH_DFX_DFX_PORT5,
 204          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 205           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 206         // DFX_PORT6 (GPIO_61)
 207         {SOUTH_DFX_DFX_PORT6,
 208          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 209           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 210         // DFX_PORT7 (GPIO_62)
 211         {SOUTH_DFX_DFX_PORT7,
 212          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 213           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 214         // DFX_PORT8 (GPIO_63)
 215         {SOUTH_DFX_DFX_PORT8,
 216          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 217           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 218         // DFX_PORT9 (GPIO_134)
 219         {SOUTH_DFX_DFX_PORT9,
 220          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 221           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 222         // DFX_PORT10 (GPIO_135)
 223         {SOUTH_DFX_DFX_PORT10,
 224          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 225           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 226         // DFX_PORT11 (GPIO_136)
 227         {SOUTH_DFX_DFX_PORT11,
 228          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 229           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 230         // DFX_PORT12 (GPIO_137)
 231         {SOUTH_DFX_DFX_PORT12,
 232          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 233           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 234         // DFX_PORT13 (GPIO_138)
 235         {SOUTH_DFX_DFX_PORT13,
 236          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 237           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 238         // DFX_PORT14 (GPIO_139)
 239         {SOUTH_DFX_DFX_PORT14,
 240          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 241           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 242         // DFX_PORT15 (GPIO_140)
 243         {SOUTH_DFX_DFX_PORT15,
 244          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 245           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 246         // SPI_TPM_CS_N (GPIO_12)
 247         {SOUTH_GROUP0_GPIO_12,
 248          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 249           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 250         // SMB5_GBE_ALRT_N (GPIO_13)
 251         {SOUTH_GROUP0_SMB5_GBE_ALRT_N,
 252          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 253           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 254         // SMI (GPIO_98)
 255         {SOUTH_GROUP0_PCIE_CLKREQ5_N,
 256          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 257           GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 258         // NMI (GPIO_99)
 259         {SOUTH_GROUP0_PCIE_CLKREQ6_N,
 260          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 261           GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 262         // GBE3_LED0 (GPIO_100)
 263         {SOUTH_GROUP0_PCIE_CLKREQ7_N,
 264          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 265           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 266         // UART0_RXD (GPIO_101)
 267         {SOUTH_GROUP0_UART0_RXD,
 268          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 269           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 270         // UART0_TXD (GPIO_102)
 271         {SOUTH_GROUP0_UART0_TXD,
 272          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 273           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 274         // SMB5_GBE_CLK (GPIO_103)
 275         {SOUTH_GROUP0_SMB5_GBE_CLK,
 276          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 277           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 278         // SMB_GBE_DATA (GPIO_104)
 279         {SOUTH_GROUP0_SMB5_GBE_DATA,
 280          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 281           GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
 282         // ERROR2_N (GPIO_105)
 283         {SOUTH_GROUP0_ERROR2_N,
 284          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 285           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 286         // ERROR1_N (GPIO_106)
 287         {SOUTH_GROUP0_ERROR1_N,
 288          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 289           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 290         // ERROR0_N (GPIO_107)
 291         {SOUTH_GROUP0_ERROR0_N,
 292          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 293           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 294         // IERR_N (CATERR_N) (GPIO_108)
 295         {SOUTH_GROUP0_IERR_N,
 296          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 297           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 298         // MCERR_N  (GPIO_109)
 299         {SOUTH_GROUP0_MCERR_N,
 300          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 301           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 302         // SMB0_LEG_CLK (GPIO_110)
 303         {SOUTH_GROUP0_SMB0_LEG_CLK,
 304          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 305           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 306         // SMB0_LEG_DATA (GPIO_111)
 307         {SOUTH_GROUP0_SMB0_LEG_DATA,
 308          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 309           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 310         // SMB0_LEG_ALRT_N (GPIO_112)
 311         {SOUTH_GROUP0_SMB0_LEG_ALRT_N,
 312          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 313           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 314         // SMB1_HOST_DATA (GPIO_113)
 315         {SOUTH_GROUP0_SMB1_HOST_DATA,
 316          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 317           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 318         // SMB1_HOST_CLK (GPIO_114)
 319         {SOUTH_GROUP0_SMB1_HOST_CLK,
 320          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 321           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 322         // SMB2_PECI_DATA (GPIO_115)
 323         {SOUTH_GROUP0_SMB2_PECI_DATA,
 324          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 325           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 326         // SMB2_PECI_CLK (GPIO_116)
 327         {SOUTH_GROUP0_SMB2_PECI_CLK,
 328          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 329           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 330         // SMB4_CSME0_DATA (GPIO_117)
 331         {SOUTH_GROUP0_SMB4_CSME0_DATA,
 332          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 333           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 334         // SMB4_CSME0_CLK (GPIO_118)
 335         {SOUTH_GROUP0_SMB4_CSME0_CLK,
 336          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 337           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 338         // SMB4_CSME0_ALRT_N (GPIO_119)
 339         {SOUTH_GROUP0_SMB4_CSME0_ALRT_N,
 340          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 341           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 342         // USB_OC0_N (GPIO_120)
 343         {SOUTH_GROUP0_USB_OC0_N,
 344          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 345           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 346         // FLEX_CLK_SE0 (GPIO_121)
 347         {SOUTH_GROUP0_FLEX_CLK_SE0,
 348          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 349           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 350         // FLEX_CLK_SE1 (GPIO_122)
 351         {SOUTH_GROUP0_FLEX_CLK_SE1,
 352          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 353           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 354         // GBE3_LED1 (GPIO_4)
 355         {SOUTH_GROUP0_GPIO_4,
 356          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 357           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 358         // SMB3_IE0_CLK (GPIO_5)
 359         {SOUTH_GROUP0_GPIO_5,
 360          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 361           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 362         // SMB3_IE0_DATA (GPIO_6)
 363         {SOUTH_GROUP0_GPIO_6,
 364          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 365           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 366         // SMB3_IE0_ALERT_N (GPIO_7)
 367         {SOUTH_GROUP0_GPIO_7,
 368          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 369           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 370         // SATA0_LED (GPIO_90)
 371         {SOUTH_GROUP0_SATA0_LED_N,
 372          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 373           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 374         // SATA1_LED (GPIO_91)
 375         {SOUTH_GROUP0_SATA1_LED_N,
 376          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 377           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 378         // SATA_PDETECT0 (GPIO_92)
 379         {SOUTH_GROUP0_SATA_PDETECT0,
 380          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 381           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 382         // SATA_PDETECT1 (GPIO_93)
 383         {SOUTH_GROUP0_SATA_PDETECT1,
 384          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 385           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 386         // UART1_RTS (GPIO_94)
 387         {SOUTH_GROUP0_SATA0_SDOUT,
 388          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 389           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 390         // UART1_CTS (GPIO_95)
 391         {SOUTH_GROUP0_SATA1_SDOUT,
 392          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 393           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 394         // UART1_RXD (GPIO_96)
 395         {SOUTH_GROUP0_UART1_RXD,
 396          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 397           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 398         // UART1_TXD (GPIO_97)
 399         {SOUTH_GROUP0_UART1_TXD,
 400          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 401           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 402         // SMB6_CSME1_DATA (GPIO_8)
 403         {SOUTH_GROUP0_GPIO_8,
 404          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 405           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 406         // SMB6_CSME1_CLK (GPIO_9)
 407         {SOUTH_GROUP0_GPIO_9,
 408          {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 409           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 410         // TCK (GPIO_141)
 411         {SOUTH_GROUP0_TCK,
 412          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 413           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 414         // TRST_N (GPIO_142)
 415         {SOUTH_GROUP0_TRST_N,
 416          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 417           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 418         // TMS (GPIO_143)
 419         {SOUTH_GROUP0_TMS,
 420          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 421           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 422         // TDI (GPIO_144)
 423         {SOUTH_GROUP0_TDI,
 424          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 425           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 426         // TDO (GPIO_145)
 427         {SOUTH_GROUP0_TDO,
 428          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 429           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 430         // CX_PRDY_N (GPIO_146)
 431         {SOUTH_GROUP0_CX_PRDY_N,
 432          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 433           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 434         // CX-PREQ_N (GPIO_147)
 435         {SOUTH_GROUP0_CX_PREQ_N,
 436          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 437           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 438         // ME_RECVR_HDR (GPIO_148)
 439         {SOUTH_GROUP0_CTBTRIGINOUT,
 440          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 441           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 442         // ADV_DBG_DFX_HDR (GPIO_149)
 443         {SOUTH_GROUP0_CTBTRIGOUT,
 444          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 445           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 446         // LAD2_SPI_IRQ_N (GPIO_150)
 447         {SOUTH_GROUP0_DFX_SPARE2,
 448          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 449           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 450         // SMB_PECI_ALRT_N (GPIO_151)
 451         {SOUTH_GROUP0_DFX_SPARE3,
 452          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 453           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 454         // SMB_CSME1_ALRT_N (GPIO_152)
 455         {SOUTH_GROUP0_DFX_SPARE4,
 456          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 457           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 458         // SUSPWRDNACK (GPIO_79)
 459         {SOUTH_GROUP1_SUSPWRDNACK,
 460          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 461           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 462         // PMU_SUSCLK (GPIO_80)
 463         {SOUTH_GROUP1_PMU_SUSCLK,
 464          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 465           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 466         // ADR_TRIGGER_N (GPIO_81)
 467         {SOUTH_GROUP1_ADR_TRIGGER,
 468          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 469           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 470         // PMU_SLP_S45_N (GPIO_82)
 471         {SOUTH_GROUP1_PMU_SLP_S45_N,
 472          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 473           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 474         // PMU_SLP_S3_N (GPIO_83)
 475         {SOUTH_GROUP1_PMU_SLP_S3_N,
 476          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 477           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 478         // PMU_WAKE_N (GPIO_84)
 479         {SOUTH_GROUP1_PMU_WAKE_N,
 480          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 481           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 482         // PMU_PWRBTN_N (GPIO_85)
 483         {SOUTH_GROUP1_PMU_PWRBTN_N,
 484          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 485           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 486         // PMU_RESETBUTTON_N (GPIO_86)
 487         {SOUTH_GROUP1_PMU_RESETBUTTON_N,
 488          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 489           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 490         // PMU_PLTRST_N (GPIO_87)
 491         {SOUTH_GROUP1_PMU_PLTRST_N,
 492          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 493           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 494         // PMU_SUS_STAT_N (GPIO_88)
 495         {SOUTH_GROUP1_SUS_STAT_N,
 496          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 497           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 498         // TDB_CIO_PLUG_EVENT (GPIO_89)
 499         {SOUTH_GROUP1_SLP_S0IX_N,
 500          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 501           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 502         // SPI_CS0_N (GPIO_72)
 503         {SOUTH_GROUP1_SPI_CS0_N,
 504          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 505           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 506         // SPI_CS1_N (GPIO_73)
 507         {SOUTH_GROUP1_SPI_CS1_N,
 508          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 509           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 510         // SPI_MOSI_IO0 (GPIO_74)
 511         {SOUTH_GROUP1_SPI_MOSI_IO0,
 512          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 513           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 514         // SPI_MISO_IO1 (GPIO_75)
 515         {SOUTH_GROUP1_SPI_MISO_IO1,
 516          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 517           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 518         // SPI_IO2 (GPIO_76)
 519         {SOUTH_GROUP1_SPI_IO2,
 520          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 521           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 522         // SPI_IO3 (GPIO_77)
 523         {SOUTH_GROUP1_SPI_IO3,
 524          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 525           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 526         // SPI_CLK (GPIO_78)
 527         {SOUTH_GROUP1_SPI_CLK,
 528          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 529           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 530         // LPC_AD0 (GPIO_64)
 531         {SOUTH_GROUP1_ESPI_IO0,
 532          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 533           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 534         // LPC_AD1 (GPIO_65)
 535         {SOUTH_GROUP1_ESPI_IO1,
 536          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 537           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 538         // LPC_AD2 (GPIO_66)
 539         {SOUTH_GROUP1_ESPI_IO2,
 540          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 541           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 542         // LPC_AD3 (GPIO_67)
 543         {SOUTH_GROUP1_ESPI_IO3,
 544          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 545           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 546         // LPC_FRAME_N (GPIO_68)
 547         {SOUTH_GROUP1_ESPI_CS0_N,
 548          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 549           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 550         // LPC_CLKOUT0 (GPIO_69)
 551         {SOUTH_GROUP1_ESPI_CLK,
 552          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 553           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 554         // LPC_CLKOUT1 (GPIO_70)
 555         {SOUTH_GROUP1_ESPI_RST_N,
 556          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 557           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 558         // LPC_CLKRUN_N (GPIO_71)
 559         {SOUTH_GROUP1_ESPI_ALRT0_N,
 560          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 561           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 562         // MFG_MODE_HDR (GPIO_10)
 563         {SOUTH_GROUP1_GPIO_10,
 564          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
 565           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 566         // LPC_SERIRQ (GPIO_11)
 567         {SOUTH_GROUP1_GPIO_11,
 568          {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 569           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 570         // EMMC-CMD (GPIO_123)
 571         {SOUTH_GROUP1_EMMC_CMD,
 572          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 573           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 574         // EMMC-CSTROBE (GPIO_124)
 575         {SOUTH_GROUP1_EMMC_STROBE,
 576          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 577           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 578         // EMMC-CLK (GPIO_125)
 579         {SOUTH_GROUP1_EMMC_CLK,
 580          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 581           GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },
 582         // EMMC-D0 (GPIO_126)
 583         {SOUTH_GROUP1_EMMC_D0,
 584          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 585           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 586         // EMMC-D1 (GPIO_127)
 587         {SOUTH_GROUP1_EMMC_D1,
 588          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 589           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 590         // EMMC-D2 (GPIO_128)
 591         {SOUTH_GROUP1_EMMC_D2,
 592          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 593           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 594         // EMMC-D3 (GPIO_129)
 595         {SOUTH_GROUP1_EMMC_D3,
 596          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 597           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 598         // EMMC-D4 (GPIO_130)
 599         {SOUTH_GROUP1_EMMC_D4,
 600          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 601           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 602         // EMMC-D5 (GPIO_131)
 603         {SOUTH_GROUP1_EMMC_D5,
 604          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 605           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 606         // EMMC-D6 (GPIO_132)
 607         {SOUTH_GROUP1_EMMC_D6,
 608          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 609           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 610         // EMMC-D7 (GPIO_133)
 611         {SOUTH_GROUP1_EMMC_D7,
 612          {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
 613           GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
 614         // IE_ROM GPIO (GPIO_3)
 615         {SOUTH_GROUP1_GPIO_3,
 616          {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
 617           GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
 618 };
 619 #endif
 620
 621 #endif /* _MAINBOARD_GPIO_H */