?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
soc/intel: Remove blank lines before '}' and after '{'
[coreboot2.git] / src / mainboard / intel / kunimitsu / devicetree.cb
blob0d9331b7c010073e7281325a9eb9ee040f34244c
1 chip soc/intel/skylake
2
3 # Enable deep Sx states
4 register "deep_s5_enable_ac" = "1"
5 register "deep_s5_enable_dc" = "1"
6 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
7
8 # GPE configuration
9 # Note that GPE events called out in ASL code rely on this
10 # route. i.e. If this route changes then the affected GPE
11 # offset bits also need to be changed.
12 register "gpe0_dw0" = "GPP_B"
13 register "gpe0_dw1" = "GPP_D"
14 register "gpe0_dw2" = "GPP_E"
15
16 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
17 register "gen1_dec" = "0x00fc0801"
18 register "gen2_dec" = "0x000c0201"
19
20 # Enable DPTF
21 register "dptf_enable" = "1"
22
23 # FSP Configuration
24 register "DspEnable" = "1"
25 register "IoBufferOwnership" = "3"
26 register "ScsEmmcHs400Enabled" = "1"
27 register "SkipExtGfxScan" = "1"
28 register "SaGv" = "SaGv_Enabled"
29
30 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
31 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
32 register "PmConfigSlpS3MinAssert" = "0x02"
33
34 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
35 register "PmConfigSlpS4MinAssert" = "0x04"
36
37 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
38 register "PmConfigSlpSusMinAssert" = "0x03"
39
40 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
41 register "PmConfigSlpAMinAssert" = "0x03"
42
43
44 # VR Settings Configuration for 4 Domains
45 #+----------------+-----------+-----------+-------------+----------+
46 #| Domain/Setting | SA | IA | GT Unsliced | GT |
47 #+----------------+-----------+-----------+-------------+----------+
48 #| Psi1Threshold | 20A | 20A | 20A | 20A |
49 #| Psi2Threshold | 4A | 5A | 5A | 5A |
50 #| Psi3Threshold | 1A | 1A | 1A | 1A |
51 #| Psi3Enable | 1 | 1 | 1 | 1 |
52 #| Psi4Enable | 1 | 1 | 1 | 1 |
53 #| ImonSlope | 0 | 0 | 0 | 0 |
54 #| ImonOffset | 0 | 0 | 0 | 0 |
55 #| IccMax | 7A | 34A | 35A | 35A |
56 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
57 #+----------------+-----------+-----------+-------------+----------+
58 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
59 .vr_config_enable = 1,
60 .psi1threshold = VR_CFG_AMP(20),
61 .psi2threshold = VR_CFG_AMP(4),
62 .psi3threshold = VR_CFG_AMP(1),
63 .psi3enable = 1,
64 .psi4enable = 1,
65 .imon_slope = 0x0,
66 .imon_offset = 0x0,
67 .icc_max = VR_CFG_AMP(7),
68 .voltage_limit = 1520,
69 }"
70
71 register "domain_vr_config[VR_IA_CORE]" = "{
72 .vr_config_enable = 1,
73 .psi1threshold = VR_CFG_AMP(20),
74 .psi2threshold = VR_CFG_AMP(5),
75 .psi3threshold = VR_CFG_AMP(1),
76 .psi3enable = 1,
77 .psi4enable = 1,
78 .imon_slope = 0x0,
79 .imon_offset = 0x0,
80 .icc_max = VR_CFG_AMP(34),
81 .voltage_limit = 1520,
82 }"
83
84 register "domain_vr_config[VR_GT_UNSLICED]" = "{
85 .vr_config_enable = 1,
86 .psi1threshold = VR_CFG_AMP(20),
87 .psi2threshold = VR_CFG_AMP(5),
88 .psi3threshold = VR_CFG_AMP(1),
89 .psi3enable = 1,
90 .psi4enable = 1,
91 .imon_slope = 0x0,
92 .imon_offset = 0x0,
93 .icc_max = VR_CFG_AMP(35),
94 .voltage_limit = 1520,
95 }"
96
97 register "domain_vr_config[VR_GT_SLICED]" = "{
98 .vr_config_enable = 1,
99 .psi1threshold = VR_CFG_AMP(20),
100 .psi2threshold = VR_CFG_AMP(5),
101 .psi3threshold = VR_CFG_AMP(1),
102 .psi3enable = 1,
103 .psi4enable = 1,
104 .imon_slope = 0x0,
105 .imon_offset = 0x0,
106 .icc_max = VR_CFG_AMP(35),
107 .voltage_limit = 1520,
108 }"
109
110 # Enable Root port 1 and 5.
111 register "PcieRpEnable[0]" = "1"
112 register "PcieRpEnable[4]" = "1"
113 # Enable CLKREQ#
114 register "PcieRpClkReqSupport[0]" = "1"
115 register "PcieRpClkReqSupport[4]" = "1"
116 # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
117 register "PcieRpClkReqNumber[0]" = "1"
118 register "PcieRpClkReqNumber[4]" = "2"
119
120 register "usb2_ports" = "{
121 [0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */
122 [1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */
123 [2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
124 [4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */
125 [6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
126 [8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */
127 }"
128
129 register "usb3_ports" = "{
130 [0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */
131 [1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */
132 [2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */
133 [3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */
134 }"
135
136 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
137
138 # Must leave UART0 enabled or SD/eMMC will not work as PCI
139 register "SerialIoDevMode" = "{
140 [PchSerialIoIndexI2C0] = PchSerialIoPci,
141 [PchSerialIoIndexI2C1] = PchSerialIoPci,
142 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
143 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
144 [PchSerialIoIndexI2C4] = PchSerialIoPci,
145 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
146 [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
147 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
148 [PchSerialIoIndexUart0] = PchSerialIoPci,
149 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
150 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
151 }"
152
153 # PL2 override 25W
154 register "power_limits_config" = "{
155 .tdp_pl2_override = 25,
156 }"
157
158 # Send an extra VR mailbox command for the PS4 exit issue
159 register "SendVrMbxCmd" = "2"
160
161 # Use default SD card detect GPIO configuration
162 register "sdcard_cd_gpio" = "GPP_A7"
163
164 device cpu_cluster 0 on end
165 device domain 0 on
166 device ref igpu on end
167 device ref sa_thermal on end
168 device ref south_xhci on end
169 device ref thermal on end
170 device ref i2c0 on
171 chip drivers/i2c/generic
172 register "hid" = ""ELAN0001""
173 register "desc" = ""ELAN Touchscreen""
174 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
175 device i2c 10 on end
176 end
177 end
178 device ref i2c1 on
179 chip drivers/i2c/generic
180 register "hid" = ""ELAN0000""
181 register "desc" = ""ELAN Touchpad""
182 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
183 register "wake" = "GPE0_DW0_05"
184 device i2c 15 on end
185 end
186 end
187 device ref heci1 on end
188 device ref uart2 on end
189 device ref i2c4 on
190 chip drivers/i2c/nau8825
191 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
192 register "jkdet_enable" = "1"
193 register "jkdet_pull_enable" = "1"
194 register "jkdet_pull_up" = "1"
195 register "jkdet_polarity" = "1" # ActiveLow
196 register "vref_impedance" = "2" # 125kOhm
197 register "micbias_voltage" = "6" # 2.754
198 register "sar_threshold_num" = "4"
199 register "sar_threshold[0]" = "0x08"
200 register "sar_threshold[1]" = "0x12"
201 register "sar_threshold[2]" = "0x26"
202 register "sar_threshold[3]" = "0x73"
203 register "sar_hysteresis" = "0"
204 register "sar_voltage" = "6"
205 register "sar_compare_time" = "1" # 1us
206 register "sar_sampling_time" = "1" # 4us
207 register "short_key_debounce" = "3" # 30ms
208 register "jack_insert_debounce" = "7" # 512ms
209 register "jack_eject_debounce" = "0"
210 device i2c 1a on end
211 end
212 chip drivers/i2c/generic
213 register "hid" = ""INT343B""
214 register "desc" = ""SSM4567 Left Speaker Amp""
215 register "uid" = "0"
216 register "device_present_gpio" = "GPP_E3"
217 device i2c 34 on end
218 end
219 chip drivers/i2c/generic
220 register "hid" = ""INT343B""
221 register "desc" = ""SSM4567 Right Speaker Amp""
222 register "uid" = "1"
223 register "device_present_gpio" = "GPP_E3"
224 device i2c 35 on end
225 end
226 end
227 device ref pcie_rp1 on
228 chip drivers/wifi/generic
229 register "wake" = "GPE0_DW0_16"
230 device pci 00.0 on end
231 end
232 end
233 device ref pcie_rp5 on end
234 device ref uart0 on end
235 device ref emmc on end
236 device ref sdxc on end
237 device ref lpc_espi on
238 chip drivers/pc80/tpm
239 device pnp 0c31.0 on end
240 end
241 chip ec/google/chromeec
242 device pnp 0c09.0 on end
243 end
244 end
245 device ref hda on
246 chip drivers/generic/max98357a
247 register "hid" = ""MX98357A""
248 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
249 register "device_present_gpio" = "GPP_E3"
250 register "device_present_gpio_invert" = "1"
251 device generic 0 on end
252 end
253 end
254 device ref smbus on end
255 device ref fast_spi on end
256 end
257 end
coreboot repo mirror