src/mainboard/kontron/986lcd-m/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pci_ops.h>
   5 #include <device/pnp_ops.h>
   6 #include <device/pnp_def.h>
   7 #include <option.h>
   8 #include <northbridge/intel/i945/i945.h>
   9 #include <southbridge/intel/i82801gx/i82801gx.h>
  10 #include <superio/winbond/common/winbond.h>
  11 #include <superio/winbond/w83627thg/w83627thg.h>
  12
  13 /* Override the default lpc decode ranges */
  14 void mainboard_lpc_decode(void)
  15 {
  16         int lpt_en = 0;
  17
  18         if (get_uint_option("lpt", 0))
  19                 lpt_en = LPT_LPC_EN; /* enable LPT */
  20
  21         pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
  22 }
  23
  24 /* This box has two superios, so enabling serial becomes slightly excessive.
  25  * We disable a lot of stuff to make sure that there are no conflicts between
  26  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
  27  * but safe anyways" method.
  28  */
  29 void bootblock_mainboard_early_init(void)
  30 {
  31         pnp_devfn_t dev;
  32
  33         dev = PNP_DEV(0x2e, W83627THG_SP1);
  34         pnp_enter_conf_state(dev);
  35
  36         pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */
  37
  38         pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */
  39         pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */
  40
  41         dev = PNP_DEV(0x2e, W83627THG_SP1);
  42         pnp_set_logical_device(dev);
  43         pnp_set_enable(dev, 0);
  44         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
  45         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
  46         pnp_set_enable(dev, 1);
  47
  48         dev = PNP_DEV(0x2e, W83627THG_SP2);
  49         pnp_set_logical_device(dev);
  50         pnp_set_enable(dev, 0);
  51         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
  52         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
  53         pnp_set_enable(dev, 1);
  54
  55         dev = PNP_DEV(0x2e, W83627THG_KBC);
  56         pnp_set_logical_device(dev);
  57         pnp_set_enable(dev, 0);
  58         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
  59         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
  60         pnp_set_enable(dev, 1);
  61
  62         dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
  63         pnp_set_logical_device(dev);
  64         pnp_set_enable(dev, 0);
  65         pnp_write_config(dev, PNP_IDX_MSC5, 0xff); /* invert all GPIOs */
  66         pnp_set_enable(dev, 1);
  67
  68         dev = PNP_DEV(0x2e, W83627THG_GPIO2);
  69         pnp_set_logical_device(dev);
  70         pnp_set_enable(dev, 1); /* Just enable it */
  71
  72         dev = PNP_DEV(0x2e, W83627THG_GPIO3);
  73         pnp_set_logical_device(dev);
  74         pnp_set_enable(dev, 0);
  75         pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); /* GPIO bit 2 is output */
  76         pnp_write_config(dev, PNP_IDX_MSC1, 0x00); /* GPIO bit 2 is 0 */
  77         /* Enable GPIO3+4. pnp_set_enable is not sufficient */
  78         pnp_write_config(dev, PNP_IDX_EN, 0x03);
  79
  80         dev = PNP_DEV(0x2e, W83627THG_FDC);
  81         pnp_set_logical_device(dev);
  82         pnp_set_enable(dev, 0);
  83
  84         dev = PNP_DEV(0x2e, W83627THG_PP);
  85         pnp_set_logical_device(dev);
  86         pnp_set_enable(dev, 0);
  87
  88         /* Enable HWM */
  89         dev = PNP_DEV(0x2e, W83627THG_HWM);
  90         pnp_set_logical_device(dev);
  91         pnp_set_enable(dev, 0);
  92         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
  93         pnp_set_enable(dev, 1);
  94
  95         pnp_exit_conf_state(dev);
  96
  97         dev = PNP_DEV(0x4e, W83627THG_SP1);
  98         pnp_enter_conf_state(dev);
  99
 100         pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */
 101         pnp_set_enable(dev, 0);
 102         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
 103         pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
 104         pnp_set_enable(dev, 1);
 105
 106         dev = PNP_DEV(0x4e, W83627THG_SP2);
 107         pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */
 108         pnp_set_enable(dev, 0);
 109         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
 110         pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
 111         pnp_set_enable(dev, 1);
 112
 113         dev = PNP_DEV(0x4e, W83627THG_FDC);
 114         pnp_set_logical_device(dev);
 115         pnp_set_enable(dev, 0);
 116
 117         dev = PNP_DEV(0x4e, W83627THG_PP);
 118         pnp_set_logical_device(dev);
 119         pnp_set_enable(dev, 0);
 120
 121         dev = PNP_DEV(0x4e, W83627THG_KBC);
 122         pnp_set_logical_device(dev);
 123         pnp_set_enable(dev, 0);
 124         pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
 125         pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
 126
 127         pnp_exit_conf_state(dev);
 128 }
 129
 130 void mainboard_late_rcba_config(void)
 131 {
 132         /* Device 1f interrupt pin register */
 133         RCBA32(D31IP) = 0x00042210;
 134         /* Device 1d interrupt pin register */
 135         RCBA32(D28IP) = 0x00214321;
 136
 137         /* dev irq route register */
 138         RCBA16(D31IR) = 0x0132;
 139         RCBA16(D30IR) = 0x3241;
 140         RCBA16(D29IR) = 0x0237;
 141         RCBA16(D28IR) = 0x3210;
 142         RCBA16(D27IR) = 0x3210;
 143
 144         /* Enable PCIe Root Port Clock Gate */
 145 }