src/mainboard/kontron/ktqm77/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pnp_def.h>
   5 #include <device/pnp_ops.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci_def.h>
   8 #include <northbridge/intel/sandybridge/raminit.h>
   9 #include <northbridge/intel/sandybridge/sandybridge.h>
  10 #include <southbridge/intel/bd82x6x/pch.h>
  11 #include <southbridge/intel/common/gpio.h>
  12 #include <superio/winbond/common/winbond.h>
  13
  14 void mainboard_pch_lpc_setup(void)
  15 {
  16         /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
  17         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
  18
  19         /* Enable KBC on 0x06/0x64 (KBC),
  20          *        EC on 0x62/0x66 (MC),
  21          *        EC on 0x20c-0x20f (GAMEH),
  22          *        Super I/O on 0x2e/0x2f (CNF1),
  23          *        COM1/COM3 decode ranges. */
  24         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  25                            KBC_LPC_EN | MC_LPC_EN |
  26                            CNF1_LPC_EN | GAMEH_LPC_EN |
  27                            COMA_LPC_EN | COMB_LPC_EN);
  28 }
  29
  30 void bootblock_mainboard_early_init(void)
  31 {
  32         int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
  33         int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
  34         const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
  35         pnp_enter_conf_state(dev);
  36         pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
  37         pnp_write_config(dev, PNP_IDX_EN, 0x03); /* Enable GPIO2+3 */
  38         pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are
  39                                               GPIO27, 26, 25, 24 */
  40         pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32,
  41                                               Pins 78~85 are UART B */
  42         pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are
  43                                               GPIO57~50 */
  44         pnp_set_logical_device(dev);
  45         /* Values can only be changed, when devices are enabled. */
  46         pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */
  47         pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */
  48         /* Disable suspend LED during normal operation */
  49         pnp_write_config(dev, PNP_IDX_MSC3, 0x40);
  50         pnp_exit_conf_state(dev);
  51 }
  52
  53 void mainboard_fill_pei_data(struct pei_data *pei_data)
  54 {
  55 }
  56
  57 const struct southbridge_usb_port mainboard_usb_ports[] = {
  58         /* enabled power  USB oc pin  */
  59         { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
  60         { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
  61         { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
  62         { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */
  63         { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */
  64         { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */
  65         { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */
  66         { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */
  67         { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */
  68         { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */
  69         { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */
  70         { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */
  71         { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */
  72         { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */
  73 };
  74
  75 void mainboard_early_init(int s3resume)
  76 {
  77         /* Enable PEG10 (1x16) */
  78         pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
  79                            pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
  80                            DEVEN_PEG10);
  81 }