src/mainboard/kontron/ktqm77/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef KTQM77_GPIO_H
   4 #define KTQM77_GPIO_H
   5
   6 #include <southbridge/intel/common/gpio.h>
   7
   8 /*
   9  * TODO: Investigate somehow... Current values are taken from a running
  10  *       system with vendor supplied firmware.
  11  */
  12
  13 static const struct pch_gpio_set1 pch_gpio_set1_mode = {
  14         .gpio0  = GPIO_MODE_GPIO,   /* Unknown Input */
  15         .gpio1  = GPIO_MODE_GPIO,   /* Unknown Input */
  16         .gpio2  = GPIO_MODE_GPIO,   /* Unknown Input */
  17         .gpio3  = GPIO_MODE_GPIO,   /* Unknown Input */
  18         .gpio4  = GPIO_MODE_GPIO,   /* Unknown Input */
  19         .gpio5  = GPIO_MODE_GPIO,   /* Unknown Input */
  20         .gpio6  = GPIO_MODE_GPIO,   /* Unknown Input */
  21         .gpio7  = GPIO_MODE_GPIO,   /* Unknown Input */
  22         .gpio8  = GPIO_MODE_GPIO,   /* Unknown Output LOW*/
  23         .gpio9  = GPIO_MODE_NATIVE, /* Native - OC5# pin */
  24         .gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */
  25         .gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */
  26         .gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */
  27         .gpio13 = GPIO_MODE_GPIO,   /* Unknown Input */
  28         .gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */
  29         .gpio15 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
  30         .gpio16 = GPIO_MODE_GPIO,   /* Unknown Input */
  31         .gpio17 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
  32         .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */
  33         .gpio19 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
  34         .gpio20 = GPIO_MODE_GPIO,   /* Unknown Input */
  35         .gpio21 = GPIO_MODE_GPIO,   /* Unknown Input */
  36         .gpio22 = GPIO_MODE_GPIO,   /* Unknown Input */
  37         .gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */
  38         .gpio24 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
  39         .gpio25 = GPIO_MODE_GPIO,   /* Unknown Input */
  40         .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */
  41         .gpio27 = GPIO_MODE_GPIO,   /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally
  42                                                            when going to suspend (S3, S4, S5). */
  43         .gpio28 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
  44         .gpio29 = GPIO_MODE_NATIVE,   /* Native - SLP_LAN# pin, forced by soft strap */
  45         .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */
  46         .gpio31 = GPIO_MODE_NATIVE  /* Native - ACPRESENT */
  47 };
  48
  49 static const struct pch_gpio_set1 pch_gpio_set1_direction = {
  50         .gpio0  = GPIO_DIR_INPUT,  /* Unknown Input */
  51         .gpio1  = GPIO_DIR_INPUT,  /* Unknown Input */
  52         .gpio2  = GPIO_DIR_INPUT,  /* Unknown Input */
  53         .gpio3  = GPIO_DIR_INPUT,  /* Unknown Input */
  54         .gpio4  = GPIO_DIR_INPUT,  /* Unknown Input */
  55         .gpio5  = GPIO_DIR_INPUT,  /* Unknown Input */
  56         .gpio6  = GPIO_DIR_INPUT,  /* Unknown Input */
  57         .gpio7  = GPIO_DIR_INPUT,  /* Unknown Input */
  58         .gpio8  = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
  59         .gpio9  = GPIO_DIR_INPUT,  /* Native */
  60         .gpio10 = GPIO_DIR_INPUT,  /* Native */
  61         .gpio11 = GPIO_DIR_INPUT,  /* Native */
  62         .gpio12 = GPIO_DIR_INPUT,  /* Native */
  63         .gpio13 = GPIO_DIR_INPUT,  /* Unknown Input */
  64         .gpio14 = GPIO_DIR_INPUT,  /* Native */
  65         .gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
  66         .gpio16 = GPIO_DIR_INPUT,  /* Unknown Input */
  67         .gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
  68         .gpio18 = GPIO_DIR_INPUT,  /* Native */
  69         .gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
  70         .gpio20 = GPIO_DIR_INPUT,  /* Unknown Input */
  71         .gpio21 = GPIO_DIR_INPUT,  /* Unknown Input */
  72         .gpio22 = GPIO_DIR_INPUT,  /* Unknown Input */
  73         .gpio23 = GPIO_DIR_INPUT,  /* Native */
  74         .gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
  75         .gpio25 = GPIO_DIR_INPUT,  /* Unknown Input */
  76         .gpio26 = GPIO_DIR_INPUT,  /* Native */
  77         .gpio27 = GPIO_DIR_INPUT,  /* Unknown Input */
  78         .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
  79         .gpio29 = GPIO_DIR_INPUT,  /* Native */
  80         .gpio30 = GPIO_DIR_INPUT,  /* Native */
  81         .gpio31 = GPIO_DIR_INPUT,  /* Native */
  82 };
  83
  84 static const struct pch_gpio_set1 pch_gpio_set1_level = {
  85         .gpio0  = GPIO_LEVEL_LOW,  /* Unknown Input */
  86         .gpio1  = GPIO_LEVEL_LOW,  /* Unknown Input */
  87         .gpio2  = GPIO_LEVEL_LOW,  /* Unknown Input */
  88         .gpio3  = GPIO_LEVEL_LOW,  /* Unknown Input */
  89         .gpio4  = GPIO_LEVEL_LOW,  /* Unknown Input */
  90         .gpio5  = GPIO_LEVEL_LOW,  /* Unknown Input */
  91         .gpio6  = GPIO_LEVEL_LOW,  /* Unknown Input */
  92         .gpio7  = GPIO_LEVEL_LOW,  /* Unknown Input */
  93         .gpio8  = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
  94         .gpio9  = GPIO_LEVEL_LOW,  /* Native */
  95         .gpio10 = GPIO_LEVEL_LOW,  /* Native */
  96         .gpio11 = GPIO_LEVEL_LOW,  /* Native */
  97         .gpio12 = GPIO_LEVEL_LOW,  /* Native */
  98         .gpio13 = GPIO_LEVEL_LOW,  /* Unknown Input */
  99         .gpio14 = GPIO_LEVEL_LOW,  /* Native */
 100         .gpio15 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 101         .gpio16 = GPIO_LEVEL_LOW,  /* Unknown Input */
 102         .gpio17 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 103         .gpio18 = GPIO_LEVEL_LOW,  /* Native */
 104         .gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 105         .gpio20 = GPIO_LEVEL_LOW,  /* Unknown Input */
 106         .gpio21 = GPIO_LEVEL_LOW,  /* Unknown Input */
 107         .gpio22 = GPIO_LEVEL_LOW,  /* Unknown Input */
 108         .gpio23 = GPIO_LEVEL_LOW,  /* Native */
 109         .gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 110         .gpio25 = GPIO_LEVEL_LOW,  /* Unknown Input */
 111         .gpio26 = GPIO_LEVEL_LOW,  /* Native */
 112         .gpio27 = GPIO_LEVEL_LOW,  /* Unknown Input */
 113         .gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 114         .gpio29 = GPIO_LEVEL_LOW,  /* Native */
 115         .gpio30 = GPIO_LEVEL_LOW,  /* Native */
 116         .gpio31 = GPIO_LEVEL_LOW,  /* Native */
 117 };
 118
 119 static const struct pch_gpio_set2 pch_gpio_set2_mode = {
 120         .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */
 121         .gpio33 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 122         .gpio34 = GPIO_MODE_GPIO,   /* Unknown Input */
 123         .gpio35 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
 124         .gpio36 = GPIO_MODE_GPIO,   /* Unknown Input */
 125         .gpio37 = GPIO_MODE_GPIO,   /* Unknown Input */
 126         .gpio38 = GPIO_MODE_GPIO,   /* Unknown Input */
 127         .gpio39 = GPIO_MODE_GPIO,   /* Unknown Input */
 128         .gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */
 129         .gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */
 130         .gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */
 131         .gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */
 132         .gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */
 133         .gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */
 134         .gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */
 135         .gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */
 136         .gpio48 = GPIO_MODE_GPIO,   /* Unknown Input */
 137         .gpio49 = GPIO_MODE_GPIO,   /* Unknown Input */
 138         .gpio50 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 139         .gpio51 = GPIO_MODE_GPIO,   /* Unknown Input */
 140         .gpio52 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
 141         .gpio53 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
 142         .gpio54 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 143         .gpio55 = GPIO_MODE_GPIO,   /* Unknown Input */
 144         .gpio56 = GPIO_MODE_GPIO,   /* Unknown Input */
 145         .gpio57 = GPIO_MODE_GPIO,   /* Unknown Input */
 146         .gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */
 147         .gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */
 148         .gpio60 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
 149         .gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/
 150         .gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */
 151         .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */
 152 };
 153
 154 static const struct pch_gpio_set2 pch_gpio_set2_direction = {
 155         .gpio32 = GPIO_DIR_INPUT,  /* Native */
 156         .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 157         .gpio34 = GPIO_DIR_INPUT,  /* Unknown Input */
 158         .gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
 159         .gpio36 = GPIO_DIR_INPUT,  /* Unknown Input */
 160         .gpio37 = GPIO_DIR_INPUT,  /* Unknown Input */
 161         .gpio38 = GPIO_DIR_INPUT,  /* Unknown Input */
 162         .gpio39 = GPIO_DIR_INPUT,  /* Unknown Input */
 163         .gpio40 = GPIO_DIR_INPUT,  /* Native */
 164         .gpio41 = GPIO_DIR_INPUT,  /* Native */
 165         .gpio42 = GPIO_DIR_INPUT,  /* Native */
 166         .gpio43 = GPIO_DIR_INPUT,  /* Native */
 167         .gpio44 = GPIO_DIR_INPUT,  /* Native */
 168         .gpio45 = GPIO_DIR_INPUT,  /* Native */
 169         .gpio46 = GPIO_DIR_INPUT,  /* Native */
 170         .gpio47 = GPIO_DIR_INPUT,  /* Native */
 171         .gpio48 = GPIO_DIR_INPUT,  /* Unknown Input */
 172         .gpio49 = GPIO_DIR_INPUT,  /* Unknown Input */
 173         .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 174         .gpio51 = GPIO_DIR_INPUT,  /* Unknown Input */
 175         .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
 176         .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
 177         .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 178         .gpio55 = GPIO_DIR_INPUT,  /* Unknown Input */
 179         .gpio56 = GPIO_DIR_INPUT,  /* Unknown Input */
 180         .gpio57 = GPIO_DIR_INPUT,  /* Unknown Input */
 181         .gpio58 = GPIO_DIR_INPUT,  /* Native */
 182         .gpio59 = GPIO_DIR_INPUT,  /* Native */
 183         .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
 184         .gpio61 = GPIO_DIR_INPUT,  /* Native */
 185         .gpio62 = GPIO_DIR_INPUT,  /* Native */
 186         .gpio63 = GPIO_DIR_INPUT,  /* Native */
 187 };
 188
 189 static const struct pch_gpio_set2 pch_gpio_set2_level = {
 190         .gpio32 = GPIO_LEVEL_LOW,  /* Native */
 191         .gpio33 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 192         .gpio34 = GPIO_LEVEL_LOW,  /* Unknown Input */
 193         .gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 194         .gpio36 = GPIO_LEVEL_LOW,  /* Unknown Input */
 195         .gpio37 = GPIO_LEVEL_LOW,  /* Unknown Input */
 196         .gpio38 = GPIO_LEVEL_LOW,  /* Unknown Input */
 197         .gpio39 = GPIO_LEVEL_LOW,  /* Unknown Input */
 198         .gpio40 = GPIO_LEVEL_LOW,  /* Native */
 199         .gpio41 = GPIO_LEVEL_LOW,  /* Native */
 200         .gpio42 = GPIO_LEVEL_LOW,  /* Native */
 201         .gpio43 = GPIO_LEVEL_LOW,  /* Native */
 202         .gpio44 = GPIO_LEVEL_LOW,  /* Native */
 203         .gpio45 = GPIO_LEVEL_LOW,  /* Native */
 204         .gpio46 = GPIO_LEVEL_LOW,  /* Native */
 205         .gpio47 = GPIO_LEVEL_LOW,  /* Native */
 206         .gpio48 = GPIO_LEVEL_LOW,  /* Unknown Input */
 207         .gpio49 = GPIO_LEVEL_LOW,  /* Unknown Input */
 208         .gpio50 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 209         .gpio51 = GPIO_LEVEL_LOW,  /* Unknown Input */
 210         .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 211         .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 212         .gpio54 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 213         .gpio55 = GPIO_LEVEL_LOW,  /* Unknown Input */
 214         .gpio56 = GPIO_LEVEL_LOW,  /* Unknown Input */
 215         .gpio57 = GPIO_LEVEL_LOW,  /* Unknown Input */
 216         .gpio58 = GPIO_LEVEL_LOW,  /* Native */
 217         .gpio59 = GPIO_LEVEL_LOW,  /* Native */
 218         .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
 219         .gpio61 = GPIO_LEVEL_LOW,  /* Native */
 220         .gpio62 = GPIO_LEVEL_LOW,  /* Native */
 221         .gpio63 = GPIO_LEVEL_LOW,  /* Native */
 222 };
 223
 224 static const struct pch_gpio_set3 pch_gpio_set3_mode = {
 225         .gpio64 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 226         .gpio65 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 227         .gpio66 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
 228         .gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */
 229         .gpio68 = GPIO_MODE_GPIO,   /* Unknown Input */
 230         .gpio69 = GPIO_MODE_GPIO,   /* Unknown Input */
 231         .gpio70 = GPIO_MODE_GPIO,   /* Unknown Input */
 232         .gpio71 = GPIO_MODE_GPIO,   /* Unknown Input */
 233         .gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */
 234         .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */
 235         .gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */
 236         .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */
 237 };
 238
 239 static const struct pch_gpio_set3 pch_gpio_set3_direction = {
 240         .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 241         .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 242         .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
 243         .gpio67 = GPIO_DIR_INPUT,  /* Native */
 244         .gpio68 = GPIO_DIR_INPUT,  /* Unknown Input */
 245         .gpio69 = GPIO_DIR_INPUT,  /* Unknown Input */
 246         .gpio70 = GPIO_DIR_INPUT,  /* Unknown Input */
 247         .gpio71 = GPIO_DIR_INPUT,  /* Unknown Input */
 248         .gpio72 = GPIO_DIR_INPUT,  /* Native */
 249         .gpio73 = GPIO_DIR_INPUT,  /* Native */
 250         .gpio74 = GPIO_DIR_INPUT,  /* Native */
 251         .gpio75 = GPIO_DIR_INPUT,  /* Native */
 252 };
 253
 254 static const struct pch_gpio_set3 pch_gpio_set3_level = {
 255         .gpio64 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 256         .gpio65 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 257         .gpio66 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
 258         .gpio67 = GPIO_LEVEL_LOW,  /* Native */
 259         .gpio68 = GPIO_LEVEL_LOW,  /* Unknown Input */
 260         .gpio69 = GPIO_LEVEL_LOW,  /* Unknown Input */
 261         .gpio70 = GPIO_LEVEL_LOW,  /* Unknown Input */
 262         .gpio71 = GPIO_LEVEL_LOW,  /* Unknown Input */
 263         .gpio72 = GPIO_LEVEL_LOW,  /* Native */
 264         .gpio73 = GPIO_LEVEL_LOW,  /* Native */
 265         .gpio74 = GPIO_LEVEL_LOW,  /* Native */
 266         .gpio75 = GPIO_LEVEL_LOW,  /* Native */
 267 };
 268
 269 const struct pch_gpio_map mainboard_gpio_map = {
 270         .set1 = {
 271                 .mode           = &pch_gpio_set1_mode,
 272                 .direction      = &pch_gpio_set1_direction,
 273                 .level          = &pch_gpio_set1_level,
 274         },
 275         .set2 = {
 276                 .mode           = &pch_gpio_set2_mode,
 277                 .direction      = &pch_gpio_set2_direction,
 278                 .level          = &pch_gpio_set2_level,
 279         },
 280         .set3 = {
 281                 .mode           = &pch_gpio_set3_mode,
 282                 .direction      = &pch_gpio_set3_direction,
 283                 .level          = &pch_gpio_set3_level,
 284         },
 285 };
 286 #endif