src/mainboard/samsung/lumpy/devicetree.cb

   1 chip northbridge/intel/sandybridge
   2         # IGD Displays
   3         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   4
   5         # Enable DisplayPort Hotplug with 6ms pulse
   6         register "gpu_dp_d_hotplug" = "0x06"
   7
   8         # Enable Panel as LVDS and configure power delays
   9         register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
  10         register "gpu_panel_power_cycle_delay" = "5"            # T4: 400ms
  11         register "gpu_panel_power_up_delay" = "400"             # T1+T2: 40ms
  12         register "gpu_panel_power_down_delay" = "150"           # T3: 15ms
  13         register "gpu_panel_power_backlight_on_delay" = "2100"  # T5: 210ms
  14         register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
  15
  16         # Set backlight PWM values
  17         register "gpu_cpu_backlight" = "0x000001e8"
  18         register "gpu_pch_backlight" = "0x03d00000"
  19
  20         register "ec_present" = "1"
  21         register "max_mem_clock_mhz" = "666"
  22
  23         register "usb_port_config" = "{
  24                 { 1, 0, 0x0080 },
  25                 { 1, 1, 0x0080 },
  26                 { 1, 0, 0x0040 },
  27                 { 1, 0, 0x0040 },
  28                 { 0, 0, 0x0000 },
  29                 { 0, 0, 0x0000 },
  30                 { 0, 0, 0x0000 },
  31                 { 0, 0, 0x0000 },
  32                 { 1, 4, 0x0040 },
  33                 { 0, 4, 0x0000 },
  34                 { 0, 4, 0x0000 },
  35                 { 1, 4, 0x0040 },
  36                 { 0, 4, 0x0000 },
  37                 { 0, 4, 0x0000 },}"
  38
  39         device domain 0 on
  40                 subsystemid 0x1ae0 0xc000 inherit
  41                 device ref host_bridge on end # host bridge
  42                 device ref igd on end # vga controller
  43
  44                 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
  45                         # GPI routing
  46                         #  0 No effect (default)
  47                         #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  48                         #  2 SCI (if corresponding GPIO_EN bit is also set)
  49                         register "alt_gp_smi_en" = "0x0002"
  50                         register "gpi1_routing" = "1"
  51                         register "gpi7_routing" = "2"
  52
  53                         register "sata_port_map" = "0x1"
  54
  55                         # EC range is 0xa00-0xa3f
  56                         register "gen1_dec" = "0x003c0a01"
  57                         register "gen2_dec" = "0x003c0b01"
  58                         register "gen3_dec" = "0x00fc1601"
  59
  60                         device ref mei1 on end # Management Engine Interface 1
  61                         device ref mei2 off end # Management Engine Interface 2
  62                         device ref me_ide_r off end # Management Engine IDE-R
  63                         device ref me_kt off end # Management Engine KT
  64                         device ref gbe off end # Intel Gigabit Ethernet
  65                         device ref ehci2 on end # USB2 EHCI #2
  66                         device ref hda on end # High Definition Audio
  67                         device ref pcie_rp1 on end # PCIe Port #1 (WLAN)
  68                         device ref pcie_rp2 off end # PCIe Port #2
  69                         device ref pcie_rp3 off end # PCIe Port #3
  70                         device ref pcie_rp4 on end # PCIe Port #4 (LAN)
  71                         device ref pcie_rp5 off end # PCIe Port #5
  72                         device ref pcie_rp6 off end # PCIe Port #6
  73                         device ref pcie_rp7 off end # PCIe Port #7
  74                         device ref pcie_rp8 off end # PCIe Port #8
  75                         device ref ehci1 on end # USB2 EHCI #1
  76                         device ref pci_bridge off end # PCI bridge
  77                         device ref lpc on # LPC bridge
  78                                 chip superio/smsc/mec1308
  79                                         device pnp 2e.1 on              # PM1
  80                                                 io 0x60 = 0xb00
  81                                         end
  82                                         device pnp 2e.2 off end         # EC1
  83                                         device pnp 2e.3 off end         # EC2
  84                                         device pnp 2e.4 off end         # UART
  85                                         device pnp 2e.7 on              # KBC
  86                                                 irq 0x70 = 1
  87                                         end
  88                                         device pnp 2e.8 on              # EC0
  89                                                 io 0x60 = 0x62
  90                                         end
  91                                         device pnp 2e.9 on              # MBX
  92                                                 io 0x60 = 0xa00
  93                                         end
  94                                 end
  95                                 chip ec/smsc/mec1308
  96                                         register "mailbox_port" = "0xa00"
  97                                         device pnp ff.1 off end
  98                                 end
  99                                 chip drivers/pc80/tpm
 100                                         device pnp 0c31.0 on end
 101                                 end
 102                         end
 103                         device ref sata1 on end # SATA Controller 1
 104                         device ref smbus on
 105                                 subsystemid 0x04B4 0x18D1
 106                         end # SMBus
 107                         device ref sata2 off end # SATA Controller 2
 108                         device ref thermal on end # Thermal
 109                 end
 110         end
 111 end