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soc/intel: Remove blank lines before '}' and after '{'
[coreboot2.git] / src / soc / intel / alderlake / chip.h
bloba490540fc5999f278969b176e268fe127b761011
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef _SOC_CHIP_H_
4 #define _SOC_CHIP_H_
5
6 #include <drivers/i2c/designware/dw_i2c.h>
7 #include <drivers/intel/gma/gma.h>
8 #include <device/pci_ids.h>
9 #include <gpio.h>
10 #include <intelblocks/cfg.h>
11 #include <intelblocks/gspi.h>
12 #include <intelblocks/power_limit.h>
13 #include <intelblocks/pcie_rp.h>
14 #include <intelblocks/tcss.h>
15 #include <intelblocks/xhci.h>
16 #include <soc/gpe.h>
17 #include <soc/pci_devs.h>
18 #include <soc/pmc.h>
19 #include <soc/serialio.h>
20 #include <soc/usb.h>
21 #include <soc/vr_config.h>
22 #include <stdint.h>
23
24 /* Define config parameters for In-Band ECC (IBECC). */
25 #define MAX_IBECC_REGIONS 8
26
27 #define MAX_HD_AUDIO_SDI_LINKS 2
28
29 /* In-Band ECC Operation Mode */
30 enum ibecc_mode {
31 IBECC_MODE_PER_REGION,
32 IBECC_MODE_NONE,
33 IBECC_MODE_ALL
34 };
35
36 struct ibecc_config {
37 bool enable;
38 enum ibecc_mode mode;
39 bool range_enable[MAX_IBECC_REGIONS];
40 uint16_t range_base[MAX_IBECC_REGIONS];
41 uint16_t range_mask[MAX_IBECC_REGIONS];
42 /* add ECC error injection if needed by a mainboard */
43 };
44
45 /* Types of different SKUs */
46 enum soc_intel_alderlake_power_limits {
47 ADL_P_142_242_282_15W_CORE,
48 ADL_P_282_442_482_28W_CORE,
49 ADL_P_682_28W_CORE,
50 ADL_P_442_482_45W_CORE,
51 ADL_P_642_682_45W_CORE,
52 ADL_M_282_12W_CORE,
53 ADL_M_282_15W_CORE,
54 ADL_M_242_CORE,
55 ADL_P_442_45W_CORE,
56 ADL_N_081_7W_CORE,
57 ADL_N_081_15W_CORE,
58 ADL_N_041_6W_CORE,
59 ADL_N_021_6W_CORE,
60 ADL_S_882_35W_CORE,
61 ADL_S_882_65W_CORE,
62 ADL_S_882_125W_CORE,
63 ADL_S_882_150W_CORE,
64 ADL_S_842_35W_CORE,
65 ADL_S_842_65W_CORE,
66 ADL_S_842_125W_CORE,
67 ADL_S_642_125W_CORE,
68 ADL_S_602_35W_CORE,
69 ADL_S_602_65W_CORE,
70 ADL_S_402_60W_CORE,
71 ADL_S_402_58W_CORE,
72 ADL_S_402_35W_CORE,
73 ADL_S_202_46W_CORE,
74 ADL_S_202_35W_CORE,
75 RPL_P_682_642_482_45W_CORE,
76 RPL_P_682_482_282_28W_CORE,
77 RPL_P_282_242_142_15W_CORE,
78 RPL_S_8161_35W_CORE,
79 RPL_S_8161_65W_CORE,
80 RPL_S_8161_95W_CORE,
81 RPL_S_8161_125W_CORE,
82 RPL_S_8161_150W_CORE,
83 RPL_S_881_35W_CORE,
84 RPL_S_881_65W_CORE,
85 RPL_S_881_125W_CORE,
86 RPL_S_681_35W_CORE,
87 RPL_S_681_65W_CORE,
88 RPL_S_681_125W_CORE,
89 RPL_S_641_35W_CORE,
90 RPL_S_641_65W_CORE,
91 RPL_S_641_125W_CORE,
92 RPL_S_801_80W_CORE,
93 RPL_S_801_95W_CORE,
94 RPL_S_401_35W_CORE,
95 RPL_S_401_58W_CORE,
96 RPL_S_401_60W_CORE,
97 RPL_S_401_65W_CORE,
98 RPL_S_201_35W_CORE,
99 RPL_S_201_46W_CORE,
100 RPL_S_201_65W_CORE,
101 RPL_HX_8_16_55W_CORE,
102 RPL_HX_8_12_55W_CORE,
103 RPL_HX_8_8_55W_CORE,
104 RPL_HX_6_8_55W_CORE,
105 RPL_HX_6_4_55W_CORE,
106 ADL_POWER_LIMITS_COUNT
107 };
108
109 /* TDP values for different SKUs */
110 enum soc_intel_alderlake_cpu_tdps {
111 TDP_6W = 6,
112 TDP_7W = 7,
113 TDP_9W = 9,
114 TDP_12W = 12,
115 TDP_15W = 15,
116 TDP_28W = 28,
117 TDP_35W = 35,
118 TDP_45W = 45,
119 TDP_46W = 46,
120 TDP_55W = 55,
121 TDP_58W = 58,
122 TDP_60W = 60,
123 TDP_65W = 65,
124 TDP_80W = 80,
125 TDP_90W = 90,
126 TDP_95W = 95,
127 TDP_125W = 125,
128 TDP_150W = 150
129 };
130
131 /* Mapping of different SKUs based on CPU ID and TDP values */
132 static const struct {
133 unsigned int cpu_id;
134 enum soc_intel_alderlake_power_limits limits;
135 enum soc_intel_alderlake_cpu_tdps cpu_tdp;
136 } cpuid_to_adl[] = {
137 { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
138 { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
139 { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
140 { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W },
141 { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W },
142 { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
143 { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
144 { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
145 { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
146 { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
147 { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W },
148 { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
149 { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
150 { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
151 { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W },
152 { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W },
153 { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
154 { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },
155 { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },
156 { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W },
157 { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W },
158 { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W },
159 { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W },
160 { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W },
161 { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W },
162 { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W },
163 { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W },
164 { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W },
165 { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W },
166 { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W },
167 { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W },
168 { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W },
169 { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W },
170 { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W },
171 { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W },
172 { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
173 { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W },
174 { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
175 { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W },
176 { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
177 { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },
178 { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W },
179 { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W },
180 { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W },
181 { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W },
182 { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W },
183 { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W },
184 { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W },
185 { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W },
186 { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W },
187 { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W },
188 { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W },
189 { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W },
190 { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W },
191 { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W },
192 { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W },
193 { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W },
194 { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W },
195 { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W },
196 { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W },
197 { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W },
198 { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W },
199 { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W },
200 { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W },
201 { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W },
202 { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W },
203 { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W },
204 { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W },
205 { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W },
206 { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W },
207 { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W },
208 { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W },
209 { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W },
210 { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W },
211 { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W },
212 { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W },
213 };
214
215 /* Types of display ports */
216 enum ddi_ports {
217 DDI_PORT_A,
218 DDI_PORT_B,
219 DDI_PORT_C,
220 DDI_PORT_1,
221 DDI_PORT_2,
222 DDI_PORT_3,
223 DDI_PORT_4,
224 DDI_PORT_COUNT,
225 };
226
227 enum ddi_port_flags {
228 DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
229 DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
230 };
231
232 /*
233 * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2,
234 * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0.
235 */
236 enum fivr_enable_states {
237 FIVR_ENABLE_S0i1_S0i2 = BIT(0),
238 FIVR_ENABLE_S0i3 = BIT(1),
239 FIVR_ENABLE_S3 = BIT(2),
240 FIVR_ENABLE_S4 = BIT(3),
241 FIVR_ENABLE_S5 = BIT(4),
242 FIVR_ENABLE_S0 = BIT(5),
243 };
244
245 /*
246 * Enable the following for External V1p05 rail
247 * BIT0: Retention active switch support
248 * BIT1: Normal Active voltage supported
249 * BIT2: Minimum active voltage supported
250 * BIT3: Minimum Retention voltage supported
251 */
252 enum fivr_voltage_supported {
253 FIVR_RET_ACTIVE_SWITCH_SUPPORT = BIT(0),
254 FIVR_VOLTAGE_NORMAL = BIT(1),
255 FIVR_VOLTAGE_MIN_ACTIVE = BIT(2),
256 FIVR_VOLTAGE_MIN_RETENTION = BIT(3),
257 };
258
259 #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \
260 FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5 | FIVR_ENABLE_S0)
261 /*
262 * The Max Pkg Cstate
263 * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,
264 * 254 - CPU Default , 255 - Auto.
265 */
266 enum pkgcstate_limit {
267 LIMIT_C0_C1 = 0,
268 LIMIT_C2 = 1,
269 LIMIT_C3 = 2,
270 LIMIT_C6 = 3,
271 LIMIT_C7 = 4,
272 LIMIT_C7S = 5,
273 LIMIT_C8 = 6,
274 LIMIT_C9 = 7,
275 LIMIT_C10 = 8,
276 LIMIT_CPUDEFAULT = 254,
277 LIMIT_AUTO = 255,
278 };
279
280 /* Bit values for use in LpmStateEnableMask. */
281 enum lpm_state_mask {
282 LPM_S0i2_0 = BIT(0),
283 LPM_S0i2_1 = BIT(1),
284 LPM_S0i2_2 = BIT(2),
285 LPM_S0i3_0 = BIT(3),
286 LPM_S0i3_1 = BIT(4),
287 LPM_S0i3_2 = BIT(5),
288 LPM_S0i3_3 = BIT(6),
289 LPM_S0i3_4 = BIT(7),
290 LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
291 | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
292 };
293
294 /*
295 * FivrSpreadSpectrum:
296 * Values
297 * 0 - 0.5%, 3 - 1%, 8 - 1.5%, 18 - 2%, 28 - 3%, 34 - 4%, 39 - 5%, 44 - 6%
298 */
299 enum fivr_spread_spectrum_ratio {
300 FIVR_SS_0_5 = 0,
301 FIVR_SS_1 = 3,
302 FIVR_SS_1_5 = 8,
303 FIVR_SS_2 = 18,
304 FIVR_SS_3 = 28,
305 FIVR_SS_4 = 34,
306 FIVR_SS_5 = 39,
307 FIVR_SS_6 = 44,
308 };
309
310 /*
311 * Slew Rate configuration for Deep Package C States for VR domain.
312 * They are fast time divided by 2.
313 * 0 - Fast/2
314 * 1 - Fast/4
315 * 2 - Fast/8
316 * 3 - Fast/16
317 */
318 enum slew_rate {
319 SLEW_FAST_2,
320 SLEW_FAST_4,
321 SLEW_FAST_8,
322 SLEW_FAST_16
323 };
324
325 struct soc_intel_alderlake_config {
326 /* Common struct containing soc config data required by common code */
327 struct soc_intel_common_config common_soc_config;
328
329 /* Common struct containing power limits configuration information */
330 struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT];
331
332 /* Gpio group routed to each dword of the GPE0 block. Values are
333 * of the form PMC_GPP_[A:U] or GPD. */
334 uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
335 uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
336 uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
337
338 /* Generic IO decode ranges */
339 uint32_t gen1_dec;
340 uint32_t gen2_dec;
341 uint32_t gen3_dec;
342 uint32_t gen4_dec;
343
344 /* Enable S0iX support */
345 bool s0ix_enable;
346 /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
347 bool tcss_d3_hot_disable;
348 /* Enable DPTF support */
349 bool dptf_enable;
350
351 /* Deep SX enable for both AC and DC */
352 bool deep_s3_enable_ac;
353 bool deep_s3_enable_dc;
354 bool deep_s5_enable_ac;
355 bool deep_s5_enable_dc;
356
357 /* Deep Sx Configuration
358 * DSX_EN_WAKE_PIN - Enable WAKE# pin
359 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
360 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
361 uint32_t deep_sx_config;
362
363 /* TCC activation offset */
364 uint32_t tcc_offset;
365
366 /* In-Band ECC (IBECC) configuration */
367 struct ibecc_config ibecc;
368
369 /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
370 * When enabled memory will be training at two different frequencies.
371 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
372 * 4:FixedPoint3, 5:Enabled */
373 enum {
374 SaGv_Disabled,
375 SaGv_FixedPoint0,
376 SaGv_FixedPoint1,
377 SaGv_FixedPoint2,
378 SaGv_FixedPoint3,
379 SaGv_Enabled,
380 } sagv;
381
382 /* Rank Margin Tool. 1:Enable, 0:Disable */
383 bool RMT;
384
385 /* USB related */
386 struct usb2_port_config usb2_ports[16];
387 struct usb3_port_config usb3_ports[10];
388 /* Wake Enable Bitmap for USB2 ports */
389 uint16_t usb2_wake_enable_bitmap;
390 /* Wake Enable Bitmap for USB3 ports */
391 uint16_t usb3_wake_enable_bitmap;
392 /* Program OC pins for TCSS */
393 struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
394
395 /* SATA related */
396 uint8_t sata_mode;
397 bool sata_salp_support;
398 bool sata_ports_enable[8];
399 bool sata_ports_dev_slp[8];
400
401 /*
402 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
403 * Default 0. Setting this to 1 disables the SATA Power Optimizer.
404 */
405 bool sata_pwr_optimize_disable;
406
407 /*
408 * SATA Port Enable Dito Config.
409 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
410 */
411 bool sata_ports_enable_dito_config[8];
412
413 /* SataPortsDmVal is the DITO multiplier. Default is 15. */
414 uint8_t sata_ports_dm_val[8];
415
416 /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
417 uint16_t sata_ports_dito_val[8];
418
419 /* Audio related */
420 bool pch_hda_audio_link_hda_enable;
421 bool pch_hda_dsp_enable;
422 bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
423
424 /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
425 enum {
426 HDA_TMODE_2T = 0,
427 HDA_TMODE_4T = 2,
428 HDA_TMODE_8T = 3,
429 HDA_TMODE_16T = 4,
430 } pch_hda_idisp_link_tmode;
431
432 /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
433 enum {
434 HDA_LINKFREQ_48MHZ = 3,
435 HDA_LINKFREQ_96MHZ = 4,
436 } pch_hda_idisp_link_frequency;
437
438 bool pch_hda_idisp_codec_enable;
439
440 struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
441 struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
442 uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
443
444 /* Gfx related */
445 enum {
446 IGD_SM_0MB = 0x00,
447 IGD_SM_32MB = 0x01,
448 IGD_SM_64MB = 0x02,
449 IGD_SM_96MB = 0x03,
450 IGD_SM_128MB = 0x04,
451 IGD_SM_160MB = 0x05,
452 IGD_SM_4MB = 0xF0,
453 IGD_SM_8MB = 0xF1,
454 IGD_SM_12MB = 0xF2,
455 IGD_SM_16MB = 0xF3,
456 IGD_SM_20MB = 0xF4,
457 IGD_SM_24MB = 0xF5,
458 IGD_SM_28MB = 0xF6,
459 IGD_SM_36MB = 0xF8,
460 IGD_SM_40MB = 0xF9,
461 IGD_SM_44MB = 0xFA,
462 IGD_SM_48MB = 0xFB,
463 IGD_SM_52MB = 0xFC,
464 IGD_SM_56MB = 0xFD,
465 IGD_SM_60MB = 0xFE,
466 } igd_dvmt50_pre_alloc;
467
468 bool skip_ext_gfx_scan;
469
470 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
471 bool eist_enable;
472
473 /* Enable C6 DRAM */
474 bool enable_c6dram;
475
476 /*
477 * SerialIO device mode selection:
478 * PchSerialIoDisabled,
479 * PchSerialIoPci,
480 * PchSerialIoHidden,
481 * PchSerialIoLegacyUart,
482 * PchSerialIoSkipInit
483 */
484 uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
485 uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
486 uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
487 /*
488 * GSPIn Default Chip Select Mode:
489 * 0:Hardware Mode,
490 * 1:Software Mode
491 */
492 uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
493 /*
494 * GSPIn Default Chip Select State:
495 * 0: Low,
496 * 1: High
497 */
498 uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
499
500 /* Enable Pch iSCLK */
501 bool pch_isclk;
502
503 /* CNVi BT Core Enable/Disable */
504 bool cnvi_bt_core;
505
506 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
507 bool cnvi_bt_audio_offload;
508
509 /*
510 * These GPIOs will be programmed by the IOM to handle biasing of the
511 * Type-C aux (SBU) signals when certain alternate modes are used.
512 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
513 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
514 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
515 * (name often contains `AUXP_DC` or `_AUX_P`).
516 */
517 struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
518
519 /*
520 * SOC Aux orientation override:
521 * This is a bitfield that corresponds to up to 4 TCSS ports on ADL.
522 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
523 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
524 * on the motherboard.
525 */
526 uint16_t tcss_aux_ori;
527
528 /*
529 * Override GPIO PM configuration:
530 * 0: Use FSP default GPIO PM program,
531 * 1: coreboot to override GPIO PM program
532 */
533 bool gpio_override_pm;
534
535 /*
536 * GPIO PM configuration: 0 to disable, 1 to enable power gating
537 * Bit 6-7: Reserved
538 * Bit 5: MISCCFG_GPSIDEDPCGEN
539 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
540 * Bit 3: MISCCFG_GPRTCDLCGEN
541 * Bit 2: MISCCFG_GSXLCGEN
542 * Bit 1: MISCCFG_GPDPCGEN
543 * Bit 0: MISCCFG_GPDLCGEN
544 */
545 uint8_t gpio_pm[TOTAL_GPIO_COMM];
546
547 /* DP config */
548 /*
549 * Port config
550 * 0:Disabled, 1:eDP, 2:MIPI DSI
551 */
552 uint8_t ddi_portA_config;
553 uint8_t ddi_portB_config;
554
555 /* Enable(1)/Disable(0) HPD/DDC */
556 uint8_t ddi_ports_config[DDI_PORT_COUNT];
557
558 /* Hybrid storage mode enable (1) / disable (0)
559 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
560 * accordingly */
561 bool hybrid_storage_mode;
562
563 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
564 /* eMMC HS400 mode */
565 bool emmc_enable_hs400_mode;
566 #endif
567
568 /*
569 * Override CPU flex ratio value:
570 * CPU ratio value controls the maximum processor non-turbo ratio.
571 * Valid Range 0 to 63.
572 *
573 * In general descriptor provides option to set default cpu flex ratio.
574 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
575 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
576 *
577 * Only override CPU flex ratio if don't want to boot with non-turbo max.
578 */
579 uint8_t cpu_ratio_override;
580
581 /*
582 * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
583 * Default 0. Setting this to 1 disables the DMI Power Optimizer.
584 */
585 bool dmi_power_optimize_disable;
586
587 /*
588 * Used to communicate the power delivery design capability of the board. This
589 * value is an enum of the available power delivery segments that are defined in
590 * the Platform Design Guide.
591 */
592 uint8_t vr_power_delivery_design;
593
594 /*
595 * Enable(1)/Disable(0) CPU Replacement check.
596 * Default 0. Setting this to 1 to check CPU replacement.
597 */
598 bool cpu_replacement_check;
599
600 /* ISA Serial Base selection. */
601 enum {
602 ISA_SERIAL_BASE_ADDR_3F8,
603 ISA_SERIAL_BASE_ADDR_2F8,
604 } isa_serial_uart_base;
605
606 /* structure containing various settings for PCH FIVRs */
607 struct {
608 bool configure_ext_fivr;
609 enum fivr_enable_states v1p05_enable_bitmap;
610 enum fivr_enable_states vnn_enable_bitmap;
611 enum fivr_enable_states vnn_sx_enable_bitmap;
612 enum fivr_voltage_supported v1p05_supported_voltage_bitmap;
613 enum fivr_voltage_supported vnn_supported_voltage_bitmap;
614 /* V1p05 Rail Voltage in mv */
615 int v1p05_voltage_mv;
616 /* Vnn Rail Voltage in mv */
617 int vnn_voltage_mv;
618 /* VnnSx Rail Voltage in mv */
619 int vnn_sx_voltage_mv;
620 /* External Icc Max for V1p05 rail in mA */
621 int v1p05_icc_max_ma;
622 /* External Icc Max for VnnSx rail in mA */
623 int vnn_icc_max_ma;
624 } ext_fivr_settings;
625
626 /* VrConfig Settings.
627 * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT.
628 */
629 struct vr_config domain_vr_config[NUM_VR_DOMAINS];
630
631 uint16_t max_dram_speed_mts;
632
633 enum {
634 SLP_S3_ASSERTION_DEFAULT,
635 SLP_S3_ASSERTION_60_US,
636 SLP_S3_ASSERTION_1_MS,
637 SLP_S3_ASSERTION_50_MS,
638 SLP_S3_ASSERTION_2_S,
639 } pch_slp_s3_min_assertion_width;
640
641 enum {
642 SLP_S4_ASSERTION_DEFAULT,
643 SLP_S4_ASSERTION_1S,
644 SLP_S4_ASSERTION_2S,
645 SLP_S4_ASSERTION_3S,
646 SLP_S4_ASSERTION_4S,
647 } pch_slp_s4_min_assertion_width;
648
649 enum {
650 SLP_SUS_ASSERTION_DEFAULT,
651 SLP_SUS_ASSERTION_0_MS,
652 SLP_SUS_ASSERTION_500_MS,
653 SLP_SUS_ASSERTION_1_S,
654 SLP_SUS_ASSERTION_4_S,
655 } pch_slp_sus_min_assertion_width;
656
657 enum {
658 SLP_A_ASSERTION_DEFAULT,
659 SLP_A_ASSERTION_0_MS,
660 SLP_A_ASSERTION_4_S,
661 SLP_A_ASSERTION_98_MS,
662 SLP_A_ASSERTION_2_S,
663 } pch_slp_a_min_assertion_width;
664
665 /*
666 * PCH PM Reset Power Cycle Duration
667 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
668 * stretch duration programmed in the following registers:
669 * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
670 * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
671 * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
672 * - PM_CFG.SLP_LAN_MIN_ASST_WDTH
673 */
674 enum {
675 POWER_CYCLE_DURATION_DEFAULT,
676 POWER_CYCLE_DURATION_1S,
677 POWER_CYCLE_DURATION_2S,
678 POWER_CYCLE_DURATION_3S,
679 POWER_CYCLE_DURATION_4S,
680 } pch_reset_power_cycle_duration;
681
682 /* Platform Power Pmax */
683 uint16_t platform_pmax;
684 /*
685 * FivrRfiFrequency
686 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
687 * 0: Auto
688 * Range varies based on XTAL clock:
689 * 0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock
690 * 0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock
691 */
692 uint32_t fivr_rfi_frequency;
693 /*
694 * FivrSpreadSpectrum
695 * Set the Spread Spectrum Range.
696 * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%.
697 * Each Range is translated to an encoded value for FIVR register.
698 * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
699 */
700 uint8_t fivr_spread_spectrum;
701 /* Enable or Disable Acoustic Noise Mitigation feature */
702 bool acoustic_noise_mitigation;
703 /*
704 * Acoustic Noise Mitigation Range. Defines the maximum Pre-Wake
705 * randomization time in micro ticks. This can be programmed only
706 * if AcousticNoiseMitigation is enabled.
707 * Range 0-255
708 */
709 uint8_t PreWake;
710 /* Disable Fast Slew Rate for Deep Package C States for VR domains */
711 bool fast_pkg_c_ramp_disable[NUM_VR_DOMAINS];
712 /*
713 * Slew Rate configuration for Deep Package C States for VR domains
714 * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values
715 */
716 uint8_t slow_slew_rate[NUM_VR_DOMAINS];
717
718 /* Energy-Performance Preference (HWP feature) */
719 bool enable_energy_perf_pref;
720 uint8_t energy_perf_pref_value;
721
722 /*
723 * Enable or Disable C1 Cstate Demotion.
724 * Default 0. Set this to 1 in order to disable C state demotion.
725 */
726 bool disable_c1_state_auto_demotion;
727
728 /*
729 * Enable or Disable PCH USB2 Phy power gating.
730 * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
731 * Workaround for Intel TA# 723158 to prevent possible display flicker.
732 */
733 bool usb2_phy_sus_pg_disable;
734
735 /*
736 * Enable or Disable Package C-state Demotion.
737 * Default is set to 0.
738 * Set this to 1 in order to disable Package C-state demotion.
739 */
740 bool disable_package_c_state_demotion;
741
742 /* Enable Enhanced C States */
743 bool enable_c1e;
744
745 /* i915 struct for GMA backlight control */
746 struct i915_gpu_controller_info gfx;
747
748 /*
749 * IGD panel configuration
750 */
751 struct i915_gpu_panel_config panel_cfg;
752
753 /*
754 * Enable or Disable Tccold Handshake
755 * Default is set to 0.
756 * Set this to 1 in order to disable Tccold Handshake
757 */
758 bool disable_dynamic_tccold_handshake;
759
760 /*
761 * Enable or Disable Reduced BasicMemoryTest size.
762 * Default is set to 0.
763 * Set this to 1 in order to reduce BasicMemoryTest size
764 */
765 bool lower_basic_mem_test_size;
766
767 /*
768 * Enable or Disable SaGV reordering operation.
769 * Default is set to 0, SaGV reordering enabled.
770 * Set this to 1 in order to disable SaGV reordering.
771 */
772 bool disable_sagv_reorder;
773
774 /*
775 * Enable or Disable hwp scalability tracking.
776 * Default is set to 1.
777 * Set this to 0 in order to disable hwp scalability tracking.
778 */
779 bool enable_hwp_scalability_tracking;
780 };
781
782 typedef struct soc_intel_alderlake_config config_t;
783
784 #endif
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