src/soc/intel/common/block/crashlog/crashlog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cbmem.h>
   4 #include <console/console.h>
   5 #include <delay.h>
   6 #include <device/mmio.h>
   7 #include <intelblocks/crashlog.h>
   8 #include <intelblocks/pmc_ipc.h>
   9 #include <string.h>
  10
  11 int __weak cl_get_cpu_record_size(void)
  12 {
  13         return 0;
  14 }
  15
  16 int __weak cl_get_pmc_record_size(void)
  17 {
  18         return 0;
  19 }
  20
  21 u32 __weak cl_get_cpu_bar_addr(void)
  22 {
  23         return 0;
  24 }
  25
  26 int __weak cl_get_ioe_record_size(void)
  27 {
  28         return 0;
  29 }
  30
  31 u32 __weak cl_get_cpu_tmp_bar(void)
  32 {
  33         return 0;
  34 }
  35
  36 u32 __weak cl_get_cpu_mb_int_addr(void)
  37 {
  38         return 0;
  39 }
  40
  41 int __weak cl_get_total_data_size(void)
  42 {
  43         return cl_get_cpu_record_size() + cl_get_pmc_record_size();
  44 }
  45
  46 bool __weak cl_pmc_sram_has_mmio_access(void)
  47 {
  48         return false;
  49 }
  50
  51 bool __weak cl_ioe_sram_has_mmio_access(void)
  52 {
  53         return false;
  54 }
  55
  56 bool __weak cpu_crashlog_support(void)
  57 {
  58         return false;
  59 }
  60
  61 bool __weak pmc_crashlog_support(void)
  62 {
  63         return false;
  64 }
  65
  66 bool __weak cl_cpu_data_present(void)
  67 {
  68         return false;
  69 }
  70
  71 bool __weak cl_pmc_data_present(void)
  72 {
  73         return false;
  74 }
  75
  76 bool __weak cl_ioe_data_present(void)
  77 {
  78         return false;
  79 }
  80
  81 __weak void reset_discovery_buffers(void) {}
  82
  83 __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {}
  84
  85 __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {}
  86
  87 __weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {}
  88
  89 pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void)
  90 {
  91         pmc_ipc_discovery_buf_t discov_buf;
  92         memset(&discov_buf, 0, sizeof(pmc_ipc_discovery_buf_t));
  93         return discov_buf;
  94 }
  95
  96 pmc_crashlog_desc_table_t __weak cl_get_pmc_descriptor_table(void)
  97 {
  98         pmc_crashlog_desc_table_t desc_tab;
  99         memset(&desc_tab, 0, sizeof(pmc_crashlog_desc_table_t));
 100         return desc_tab;
 101 }
 102
 103 cpu_crashlog_discovery_table_t __weak cl_get_cpu_discovery_table(void)
 104 {
 105         cpu_crashlog_discovery_table_t cpu_disc_tab;
 106         memset(&cpu_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
 107         return cpu_disc_tab;
 108 }
 109
 110 int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
 111 {
 112         cpu_crashlog_mailbox_t cl_mailbox_interface;
 113         u16 stall_cnt = 0;
 114
 115         do {
 116                 cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr);
 117                 udelay(CPU_CRASHLOG_WAIT_STALL);
 118                 stall_cnt++;
 119         } while ((cl_mailbox_interface.fields.busy == 1)
 120                  && stall_cnt < CPU_CRASHLOG_WAIT_TIMEOUT);
 121
 122         if ((cl_mailbox_interface.fields.busy == 1)
 123             && (stall_cnt >= CPU_CRASHLOG_WAIT_TIMEOUT)) {
 124                 printk(BIOS_ERR, "CPU crashlog mailbox timed out.\n");
 125                 return 0;
 126         }
 127
 128         return 1;
 129 }
 130
 131 int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 132 {
 133         cpu_crashlog_mailbox_t cl_mailbox_intf;
 134         u32 cl_base_addr;
 135
 136         memset(&cl_mailbox_intf, 0, sizeof(cpu_crashlog_mailbox_t));
 137
 138         cl_base_addr = cl_get_cpu_bar_addr();
 139
 140         cl_mailbox_intf.fields.command = cmd;
 141         cl_mailbox_intf.fields.param = param;
 142         cl_mailbox_intf.fields.busy = 1;
 143
 144         write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()),
 145                 cl_mailbox_intf.data);
 146
 147         cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
 148
 149         return 1;
 150 }
 151
 152 int __weak cpu_cl_clear_data(void)
 153 {
 154         return cpu_cl_mailbox_cmd(CPU_CRASHLOG_CMD_CLEAR, 0);
 155 }
 156
 157 void __weak cpu_cl_rearm(void)
 158 {
 159         /* empty implementation */
 160 }
 161
 162 void __weak cpu_cl_cleanup(void)
 163 {
 164         /* empty implementation */
 165 }
 166
 167 int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 168                                 pmc_crashlog_desc_table_t *descriptor_table)
 169 {
 170         int total_data_size = 0;
 171         descriptor_table->numb_regions = read32((u32 *)desc_table_addr);
 172         printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
 173                descriptor_table->numb_regions, desc_table_addr);
 174         for (int i = 0; i < descriptor_table->numb_regions; i++) {
 175                 if (i >= ARRAY_SIZE(descriptor_table->regions)) {
 176                         printk(BIOS_ERR, "Maximum number of PMC crashLog descriptor table exceeded (%u/%zu)\n",
 177                         descriptor_table->numb_regions,
 178                         ARRAY_SIZE(descriptor_table->regions));
 179                         break;
 180                 }
 181                 desc_table_addr += 4;
 182                 descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr));
 183                 total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 184                 printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 185                         i, descriptor_table->regions[i].bits.size,
 186                         descriptor_table->regions[i].bits.offset);
 187         }
 188         return total_data_size;
 189 }
 190
 191 bool __weak pmc_cl_discovery(void)
 192 {
 193         return false;
 194 }
 195
 196 bool __weak cpu_cl_discovery(void)
 197 {
 198         return false;
 199 }
 200
 201 int cl_pmc_re_arm_after_reset(void)
 202 {
 203         const struct pmc_ipc_buffer req = { 0 };
 204         struct pmc_ipc_buffer res;
 205         uint32_t cmd_reg;
 206         int r;
 207
 208         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 209                                 PMC_IPC_CMD_ID_CRASHLOG_RE_ARM_ON_RESET,
 210                                 PMC_IPC_CMD_SIZE_SHIFT);
 211
 212         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 213
 214         if (r < 0) {
 215                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 216                 return 0;
 217         }
 218
 219         return r;
 220 }
 221
 222 /* Sends PMC IPC to clear CrashLog from PMC SSRAM area */
 223 int cl_pmc_clear(void)
 224 {
 225         const struct pmc_ipc_buffer req = { 0 };
 226         struct pmc_ipc_buffer res;
 227         uint32_t cmd_reg;
 228         int r;
 229
 230         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 231                                 PMC_IPC_CMD_ID_CRASHLOG_ERASE,
 232                                 PMC_IPC_CMD_SIZE_SHIFT);
 233
 234         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 235
 236         if (r < 0) {
 237                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 238                 return 0;
 239         }
 240
 241         return r;
 242 }
 243
 244 /*
 245  * Sends PMC IPC to populate CrashLog on all reboot.
 246  * The SSRAM area will be cleared on G3 by PMC automatically
 247  */
 248 int cl_pmc_en_gen_on_all_reboot(void)
 249 {
 250         const struct pmc_ipc_buffer req = { 0 };
 251         struct pmc_ipc_buffer res;
 252         uint32_t cmd_reg;
 253         int r;
 254
 255         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 256                                 PMC_IPC_CMD_ID_CRASHLOG_ON_RESET,
 257                                 PMC_IPC_CMD_SIZE_SHIFT);
 258
 259         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 260
 261         if (r < 0) {
 262                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 263                 return 0;
 264         }
 265
 266         return r;
 267 }
 268
 269 bool discover_crashlog(void)
 270 {
 271         bool cpu_cl_discovered = false, pmc_cl_discovered = false;
 272
 273         reset_discovery_buffers();
 274
 275         /* PCH crashLog discovery */
 276         pmc_cl_discovered = pmc_cl_discovery();
 277
 278         /* CPU crashLog discovery */
 279         cpu_cl_discovered = cpu_cl_discovery();
 280
 281         return (cpu_cl_discovered || pmc_cl_discovered);
 282 }
 283
 284 bool cl_copy_data_from_sram(u32 src_bar,
 285                                 u32 offset,
 286                                 u32 size,
 287                                 u32 *dest_addr,
 288                                 u32 buffer_index,
 289                                 bool pmc_sram)
 290 {
 291         if (src_bar == 0) {
 292                 printk(BIOS_ERR, "Invalid bar 0x%x and offset 0x%x for %s\n",
 293                        src_bar, offset, __func__);
 294                 return false;
 295         }
 296
 297         u32 src_addr = src_bar + offset;
 298
 299         u32 data =  read32((u32 *)src_addr);
 300
 301         /* First 32bits of the record must not be 0xdeadbeef */
 302         if (data == INVALID_CRASHLOG_RECORD) {
 303                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x\n",
 304                                 data, offset, src_bar);
 305                 return false;
 306         }
 307
 308         /* PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */
 309         if (pmc_sram && !(data && !(data & BIT(31)))) {
 310                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x"
 311                         " of PMC SRAM.\n", data, offset, src_bar);
 312                 return false;
 313         }
 314         /*CPU: don't copy if 1st DWORD in first buffer is zero */
 315         if (!pmc_sram && !data && (buffer_index == 0)) {
 316                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x"
 317                         " of telemetry SRAM.\n", data, offset, src_bar);
 318                 return false;
 319         }
 320
 321         u32 copied = 0;
 322         while (copied < size) {
 323                 /* DW by DW copy: byte access to PMC SRAM not allowed */
 324                 *dest_addr = read32((u32 *)src_addr);
 325                 dest_addr++;
 326                 src_addr += 4;
 327                 copied++;
 328         }
 329         return true;
 330 }
 331
 332 cl_node_t *malloc_cl_node(size_t len)
 333 {
 334         cl_node_t *node = malloc(sizeof(cl_node_t));
 335         if (!node)
 336                 return NULL;
 337
 338         node->data = malloc(len * sizeof(u32));
 339         if (!(node->data))
 340                 return NULL;
 341
 342         node->size = len * sizeof(u32);
 343         node->next = NULL;
 344
 345         return node;
 346 }
 347
 348 void free_cl_node(cl_node_t *node)
 349 {
 350         if (!node)
 351                 return;
 352         if (node->data)
 353                 free(node->data);
 354         free(node);
 355 }
 356
 357 void __weak cl_get_pmc_sram_data(cl_node_t *head)
 358 {
 359         u32 tmp_bar_addr = cl_get_cpu_tmp_bar();
 360         u32 pmc_crashLog_size = cl_get_pmc_record_size();
 361         cl_node_t *cl_cur = head;
 362
 363         if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr)
 364                 return;
 365
 366         pmc_ipc_discovery_buf_t discovery_buf = cl_get_pmc_discovery_buf();
 367
 368         if (discovery_buf.bits.supported != 1) {
 369                 printk(BIOS_DEBUG, "PCH crashlog feature not supported.\n");
 370                 goto pmc_send_re_arm_after_reset;
 371         }
 372
 373         /* Get the size of data to copy */
 374         if (discovery_buf.bits.discov_mechanism == 1) {
 375                 if (discovery_buf.bits.base_offset & BIT(31)) {
 376                         printk(BIOS_DEBUG, "PCH discovery to be used is disabled.\n");
 377                         goto pmc_send_re_arm_after_reset;
 378                 }
 379                 printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n",
 380                                 pmc_crashLog_size);
 381         } else {
 382                 if (discovery_buf.bits.dis) {
 383                         printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n");
 384                         return;
 385                 }
 386                 pmc_crashLog_size = (discovery_buf.bits.size != 0) ?
 387                                         discovery_buf.bits.size : 0xC00;
 388                 printk(BIOS_DEBUG, "PMC crashLog size in legacy mode : 0x%X\n",
 389                                 pmc_crashLog_size);
 390         }
 391
 392         bool pmc_sram = true;
 393         pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table();
 394
 395         /* goto tail node */
 396         while (cl_cur && cl_cur->next) {
 397                 cl_cur = cl_cur->next;
 398         }
 399
 400         if (discovery_buf.bits.discov_mechanism == 1) {
 401                 for (int i = 0; i < descriptor_table.numb_regions; i++) {
 402                         cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size);
 403                         if (!cl_node) {
 404                                 printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i);
 405                                 goto pmc_send_re_arm_after_reset;
 406                         }
 407
 408                         if (cl_copy_data_from_sram(tmp_bar_addr,
 409                                                 descriptor_table.regions[i].bits.offset,
 410                                                 descriptor_table.regions[i].bits.size,
 411                                                 cl_node->data,
 412                                                 i,
 413                                                 pmc_sram)) {
 414                                 cl_cur->next = cl_node;
 415                                 cl_cur = cl_cur->next;
 416                         } else {
 417                                 pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
 418                                                         sizeof(u32);
 419                                 printk(BIOS_DEBUG, "discover mode PMC crashlog size adjusted"
 420                                                 " to: 0x%x\n", pmc_crashLog_size);
 421                                 /* free cl_node */
 422                                 free_cl_node(cl_node);
 423                         }
 424                 }
 425         } else {
 426                 cl_node_t *cl_node = malloc_cl_node(discovery_buf.bits.size);
 427                 if (!cl_node) {
 428                         printk(BIOS_DEBUG, "failed to allocate cl_node\n");
 429                         goto pmc_send_re_arm_after_reset;
 430                 }
 431
 432                 if (cl_copy_data_from_sram(tmp_bar_addr,
 433                                         discovery_buf.bits.base_offset,
 434                                         discovery_buf.bits.size,
 435                                         cl_node->data,
 436                                         0,
 437                                         pmc_sram)) {
 438                         cl_cur->next = cl_node;
 439                         cl_cur = cl_cur->next;
 440                 } else {
 441                         pmc_crashLog_size -= discovery_buf.bits.size * sizeof(u32);
 442                         printk(BIOS_DEBUG, "legacy mode PMC crashlog size adjusted to: 0x%x\n",
 443                                         pmc_crashLog_size);
 444                         /* free cl_node */
 445                         free_cl_node(cl_node);
 446                 }
 447         }
 448
 449         update_new_pmc_crashlog_size(&pmc_crashLog_size);
 450
 451 pmc_send_re_arm_after_reset:
 452         /* when bit 7 of discov cmd resp is set -> bit 2 of size field */
 453         if (discovery_buf.bits.size & BIT(2))
 454                 cl_pmc_re_arm_after_reset();
 455
 456         /* Clear the SSRAM region after copying the error log */
 457         cl_pmc_clear();
 458 }
 459
 460 void cl_get_cpu_sram_data(cl_node_t *head)
 461 {
 462         cl_node_t *cl_cur = head;
 463         u32 m_cpu_crashLog_size = cl_get_cpu_record_size();
 464         cpu_crashlog_discovery_table_t cpu_cl_disc_tab = cl_get_cpu_discovery_table();
 465
 466         if (m_cpu_crashLog_size < 1) {
 467                 printk(BIOS_DEBUG, "%s: no data to collect.\n", __func__);
 468                 return;
 469         }
 470
 471         printk(BIOS_DEBUG, "CPU crash data size: 0x%X bytes in 0x%X region(s).\n",
 472                         m_cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count);
 473
 474         /* goto tail node */
 475         while (cl_cur && cl_cur->next) {
 476                 cl_cur = cl_cur->next;
 477         }
 478
 479         for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
 480                 u32 cpu_bar_addr = cl_get_cpu_bar_addr();
 481                 bool pmc_sram = false;
 482
 483                 if (!cpu_cl_disc_tab.buffers[i].fields.size) {
 484                         continue;
 485                 }
 486
 487                 cl_node_t *cl_node = malloc_cl_node(cpu_cl_disc_tab.buffers[i].fields.size);
 488                 if (!cl_node) {
 489                         printk(BIOS_DEBUG, "failed to allocate cl_node [buffer = %d]\n", i);
 490                         return;
 491                 }
 492
 493                 if (cl_copy_data_from_sram(cpu_bar_addr,
 494                                         cpu_cl_disc_tab.buffers[i].fields.offset,
 495                                         cpu_cl_disc_tab.buffers[i].fields.size,
 496                                         cl_node->data,
 497                                         i,
 498                                         pmc_sram)) {
 499                         cl_cur->next = cl_node;
 500                         cl_cur = cl_cur->next;
 501
 502                 } else {
 503                         m_cpu_crashLog_size -= cpu_cl_disc_tab.buffers[i].fields.size
 504                                 * sizeof(u32);
 505                         free_cl_node(cl_node);
 506                         /* for CPU skip all buffers if the 1st one is not valid */
 507                         if (i == 0) {
 508                                 m_cpu_crashLog_size = 0;
 509                                 break;
 510                         }
 511                 }
 512         }
 513
 514         update_new_cpu_crashlog_size(&m_cpu_crashLog_size);
 515
 516         /* clear telemetry SRAM region */
 517         cpu_cl_clear_data();
 518         /* perform any SOC specific cleanup */
 519         cpu_cl_cleanup();
 520         /* rearm crashlog */
 521         cpu_cl_rearm();
 522 }
 523
 524 void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head)
 525 {
 526         if (pmc_crashlog_support() && cl_pmc_data_present()
 527                 && (cl_get_pmc_record_size() > 0)) {
 528                 if (CONFIG(SOC_INTEL_CRASHLOG_ON_RESET)) {
 529                         cl_pmc_en_gen_on_all_reboot();
 530                         printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n");
 531                 }
 532                 cl_get_pmc_sram_data(head);
 533         } else {
 534                 printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n");
 535         }
 536
 537         printk(BIOS_DEBUG, "m_cpu_crashLog_size : 0x%X bytes\n", cl_get_cpu_record_size());
 538
 539         if (cpu_crashlog_support() && cl_cpu_data_present()
 540                 && (cl_get_cpu_record_size() > 0)) {
 541                 printk(BIOS_DEBUG, "CPU crashLog present.\n");
 542                 cl_get_cpu_sram_data(head);
 543         } else {
 544                 printk(BIOS_DEBUG, "Skipping CPU crashLog collection. Data not present.\n");
 545         }
 546 }