1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * This file is created based on Intel Tiger Lake Processor PCH Datasheet
5 * Document number: 575857
6 * Chapter number: 4, 29
10 #include <commonlib/console/post_codes.h>
11 #include <console/console.h>
12 #include <cpu/x86/smm.h>
13 #include <device/mmio.h>
14 #include <device/pci.h>
15 #include <intelblocks/cse.h>
16 #include <intelblocks/lpc_lib.h>
17 #include <intelblocks/pcr.h>
18 #include <intelblocks/pmclib.h>
19 #include <intelblocks/systemagent.h>
20 #include <intelblocks/tco.h>
22 #include <soc/pci_devs.h>
23 #include <soc/pcr_ids.h>
25 #include <soc/smbus.h>
26 #include <soc/soc_chip.h>
27 #include <soc/systemagent.h>
28 #include <spi-generic.h>
30 static void pch_finalize(void)
35 /* TODO: Add Thermal Configuration */
37 pmc_clear_pmcon_sts();
40 static void tbt_finalize(void)
43 const struct device
*dev
;
45 /* Disable Thunderbolt PCIe root ports bus master */
46 for (i
= 0; i
< NUM_TBT_FUNCTIONS
; i
++) {
47 dev
= pcidev_path_on_root(SA_DEVFN_TBT(i
));
49 pci_dev_disable_bus_master(dev
);
53 static void soc_finalize(void *unused
)
55 printk(BIOS_DEBUG
, "Finalizing chipset.\n");
58 apm_control(APM_CNT_FINALIZE
);
60 if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT
))
63 /* Indicate finalize step with post code */
64 post_code(POSTCODE_OS_BOOT
);
67 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME
, BS_ON_ENTRY
, soc_finalize
, NULL
);
68 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD
, BS_ON_EXIT
, soc_finalize
, NULL
);