src/soc/intel/tigerlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <cpu/intel/cpu_ids.h>
   6 #include <device/device.h>
   7 #include <device/pci_ops.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <fsp/api.h>
  11 #include <fsp/ppi/mp_service_ppi.h>
  12 #include <fsp/util.h>
  13 #include <gpio.h>
  14 #include <intelblocks/cse.h>
  15 #include <intelblocks/irq.h>
  16 #include <intelblocks/lpss.h>
  17 #include <intelblocks/pmclib.h>
  18 #include <intelblocks/tcss.h>
  19 #include <intelblocks/xdci.h>
  20 #include <intelpch/lockdown.h>
  21 #include <option.h>
  22 #include <security/vboot/vboot_common.h>
  23 #include <soc/intel/common/vbt.h>
  24 #include <soc/lpm.h>
  25 #include <soc/pci_devs.h>
  26 #include <soc/ramstage.h>
  27 #include <soc/soc_chip.h>
  28 #include <soc/tcss.h>
  29 #include <string.h>
  30 #include <types.h>
  31
  32 /* THC assignment definition */
  33 #define THC_NONE        0
  34 #define THC_0           1
  35 #define THC_1           2
  36
  37 /* SATA DEVSLP idle timeout default values */
  38 #define DEF_DMVAL       15
  39 #define DEF_DITOVAL     625
  40
  41 /*
  42  * ME End of Post configuration
  43  * 0 - Disable EOP.
  44  * 1 - Send in PEI (Applicable for FSP in API mode)
  45  * 2 - Send in DXE (Not applicable for FSP in API mode)
  46  */
  47 enum {
  48         EOP_DISABLE = 0,
  49         EOP_PEI = 1,
  50         EOP_DXE = 2,
  51 };
  52
  53 /*
  54  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  55  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  56  * In order to ensure that mainboard setting does not disable L1 substates
  57  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  58  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  59  * value is set in fsp_params.
  60  * 0: Use FSP UPD default
  61  * 1: Disable L1 substates
  62  * 2: Use L1.1
  63  * 3: Use L1.2 (FSP UPD default)
  64  */
  65 static int get_l1_substate_control(enum L1_substates_control ctl)
  66 {
  67         if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
  68                 ctl = L1_SS_L1_2;
  69         return ctl - 1;
  70 }
  71
  72 static void parse_devicetree(FSP_S_CONFIG *params)
  73 {
  74         const struct soc_intel_tigerlake_config *config;
  75         config = config_of_soc();
  76
  77         for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
  78                 params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
  79
  80         for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
  81                 params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
  82                 params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
  83                 params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
  84         }
  85
  86         for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
  87                 params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
  88 }
  89
  90 /*
  91  * The FSP expects a certain list of PCI devices to be in the DevIntConfig table,
  92  * regardless of whether or not they are used by the mainboard.
  93  */
  94 static const struct slot_irq_constraints irq_constraints[] = {
  95         {
  96                 .slot = SA_DEV_SLOT_PEG,
  97                 .fns = {
  98                         FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A),
  99                         FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B),
 100                         FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C),
 101                 },
 102         },
 103         {
 104                 .slot = SA_DEV_SLOT_IGD,
 105                 .fns = {
 106                         ANY_PIRQ(SA_DEVFN_IGD),
 107                 },
 108         },
 109         {
 110                 .slot = SA_DEV_SLOT_DPTF,
 111                 .fns = {
 112                         ANY_PIRQ(SA_DEVFN_DPTF),
 113                 },
 114         },
 115         {
 116                 .slot = SA_DEV_SLOT_IPU,
 117                 .fns = {
 118                         ANY_PIRQ(SA_DEVFN_IPU),
 119                 },
 120         },
 121         {
 122                 .slot = SA_DEV_SLOT_CPU_PCIE,
 123                 .fns = {
 124                         FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE, PCI_INT_D, PIRQ_D),
 125                 },
 126         },
 127         {
 128                 .slot = SA_DEV_SLOT_TBT,
 129                 .fns = {
 130                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT0, PCI_INT_A),
 131                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT1, PCI_INT_B),
 132                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT2, PCI_INT_C),
 133                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT3, PCI_INT_D),
 134                 },
 135         },
 136         {
 137                 .slot = SA_DEV_SLOT_TCSS,
 138                 .fns = {
 139                         ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
 140                         ANY_PIRQ(SA_DEVFN_TCSS_DMA0),
 141                         ANY_PIRQ(SA_DEVFN_TCSS_DMA1),
 142                 },
 143         },
 144         {
 145                 .slot = PCH_DEV_SLOT_SIO0,
 146                 .fns = {
 147                         ANY_PIRQ(PCH_DEVFN_CT),
 148                         ANY_PIRQ(PCH_DEVFN_THC0),
 149                         ANY_PIRQ(PCH_DEVFN_THC1),
 150                 },
 151         },
 152         {
 153                 .slot = PCH_DEV_SLOT_SIO1,
 154                 .fns = {
 155                         DIRECT_IRQ(PCH_DEVFN_UART3),
 156                 },
 157         },
 158         {
 159                 .slot = PCH_DEV_SLOT_ISH,
 160                 .fns = {
 161                         DIRECT_IRQ(PCH_DEVFN_ISH),
 162                         DIRECT_IRQ(PCH_DEVFN_GSPI2),
 163                 },
 164         },
 165         {
 166                 .slot = PCH_DEV_SLOT_SIO2,
 167                 .fns = {
 168                         DIRECT_IRQ(PCH_DEVFN_GSPI3),
 169                 },
 170         },
 171         {
 172                 .slot = PCH_DEV_SLOT_XHCI,
 173                 .fns = {
 174                         ANY_PIRQ(PCH_DEVFN_XHCI),
 175                         DIRECT_IRQ(PCH_DEVFN_USBOTG),
 176                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_CNVI_WIFI, PCI_INT_A),
 177                 },
 178         },
 179         {
 180                 .slot = PCH_DEV_SLOT_SIO3,
 181                 .fns = {
 182                         DIRECT_IRQ(PCH_DEVFN_I2C0),
 183                         DIRECT_IRQ(PCH_DEVFN_I2C1),
 184                         DIRECT_IRQ(PCH_DEVFN_I2C2),
 185                         DIRECT_IRQ(PCH_DEVFN_I2C3),
 186                 },
 187         },
 188         {
 189                 .slot = PCH_DEV_SLOT_CSE,
 190                 .fns = {
 191                         ANY_PIRQ(PCH_DEVFN_CSE),
 192                         ANY_PIRQ(PCH_DEVFN_CSE_2),
 193                         ANY_PIRQ(PCH_DEVFN_CSE_IDER),
 194                         ANY_PIRQ(PCH_DEVFN_CSE_KT),
 195                         ANY_PIRQ(PCH_DEVFN_CSE_3),
 196                         ANY_PIRQ(PCH_DEVFN_CSE_4),
 197                 },
 198         },
 199         {
 200                 .slot = PCH_DEV_SLOT_SATA,
 201                 .fns = {
 202                         ANY_PIRQ(PCH_DEVFN_SATA),
 203                 },
 204         },
 205         {
 206                 .slot = PCH_DEV_SLOT_SIO4,
 207                 .fns = {
 208                         DIRECT_IRQ(PCH_DEVFN_I2C4),
 209                         DIRECT_IRQ(PCH_DEVFN_I2C5),
 210                         DIRECT_IRQ(PCH_DEVFN_UART2),
 211                 },
 212         },
 213         {
 214                 .slot = PCH_DEV_SLOT_PCIE,
 215                 .fns = {
 216                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
 217                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
 218                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
 219                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
 220                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
 221                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
 222                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
 223                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
 224                 },
 225         },
 226         {
 227                 .slot = PCH_DEV_SLOT_PCIE_1,
 228                 .fns = {
 229                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE9,  PCI_INT_A, PIRQ_A),
 230                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
 231                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
 232                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
 233                 },
 234         },
 235         {
 236                 .slot = PCH_DEV_SLOT_SIO5,
 237                 .fns = {
 238                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
 239                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
 240                         DIRECT_IRQ(PCH_DEVFN_GSPI0),
 241                         DIRECT_IRQ(PCH_DEVFN_GSPI1),
 242                 },
 243         },
 244         {
 245                 .slot = PCH_DEV_SLOT_ESPI,
 246                 .fns = {
 247                         ANY_PIRQ(PCH_DEVFN_HDA),
 248                         ANY_PIRQ(PCH_DEVFN_SMBUS),
 249                         ANY_PIRQ(PCH_DEVFN_GBE),
 250                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
 251                 },
 252         },
 253 };
 254
 255 __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config)
 256 {
 257         /* Override settings per board. */
 258 }
 259
 260 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
 261 {
 262         const struct pci_irq_entry *entry = get_cached_pci_irqs();
 263         SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
 264         size_t pch_total = 0;
 265         size_t cfg_count = 0;
 266
 267         if (!entry)
 268                 return NULL;
 269
 270         /* Count PCH devices */
 271         while (entry) {
 272                 if (is_pch_slot(entry->devfn))
 273                         ++pch_total;
 274                 entry = entry->next;
 275         }
 276
 277         /* Convert PCH device entries to FSP format */
 278         config = calloc(pch_total, sizeof(*config));
 279         entry = get_cached_pci_irqs();
 280         while (entry) {
 281                 if (!is_pch_slot(entry->devfn)) {
 282                         entry = entry->next;
 283                         continue;
 284                 }
 285
 286                 config[cfg_count].Device = PCI_SLOT(entry->devfn);
 287                 config[cfg_count].Function = PCI_FUNC(entry->devfn);
 288                 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
 289                 config[cfg_count].Irq = entry->irq;
 290                 ++cfg_count;
 291
 292                 entry = entry->next;
 293         }
 294
 295         *out_count = cfg_count;
 296
 297         return config;
 298 }
 299
 300 /* UPD parameters to be initialized before SiliconInit */
 301 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 302 {
 303         int i;
 304         uint32_t cpu_id;
 305         FSP_S_CONFIG *params = &supd->FspsConfig;
 306         struct device *dev;
 307         struct soc_intel_tigerlake_config *config;
 308         config = config_of_soc();
 309         mainboard_update_soc_chip_config(config);
 310
 311         /* Parse device tree and enable/disable Serial I/O devices */
 312         parse_devicetree(params);
 313
 314         /* Load VBT before devicetree-specific config. */
 315         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 316
 317         /* Check if IGD is present and fill Graphics init param accordingly */
 318         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 319
 320         /* Use coreboot MP PPI services if Kconfig is enabled */
 321         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 322                 params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 323
 324         /* D3Hot and D3Cold for TCSS */
 325         params->D3HotEnable = !config->TcssD3HotDisable;
 326         cpu_id = cpu_get_cpuid();
 327         if (cpu_id == CPUID_TIGERLAKE_A0)
 328                 params->D3ColdEnable = 0;
 329         else
 330                 params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
 331
 332         params->UsbTcPortEn = config->UsbTcPortEn;
 333         params->TcssAuxOri = config->TcssAuxOri;
 334
 335         /* Explicitly clear this field to avoid using defaults */
 336         memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
 337
 338
 339         /* Assign PCI IRQs */
 340         if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
 341                 die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n");
 342
 343         size_t pch_count = 0;
 344         const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
 345         params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
 346         params->NumOfDevIntConfig = pch_count;
 347         printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 348
 349         /*
 350          * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
 351          * evaluate this UPD value and skip sending command. There will be no
 352          * delay for command completion.
 353          */
 354         params->ITbtConnectTopologyTimeoutInMs = 0;
 355
 356         /* Disable TcColdOnUsbConnect */
 357         params->DisableTccoldOnUsbConnected = 1;
 358
 359         /* Chipset Lockdown */
 360         const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
 361         params->PchLockDownGlobalSmi = lockdown_by_fsp;
 362         params->PchLockDownBiosInterface = lockdown_by_fsp;
 363         params->PchUnlockGpioPads = !lockdown_by_fsp;
 364         params->RtcMemoryLock = lockdown_by_fsp;
 365         params->SkipPamLock = !lockdown_by_fsp;
 366
 367         /* coreboot will send EOP before loading payload */
 368         params->EndOfPostMessage = EOP_DISABLE;
 369
 370         /* USB */
 371         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 372                 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 373                 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 374                 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 375                 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 376                 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 377
 378                 if (config->usb2_ports[i].enable)
 379                         params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 380                 else
 381                         params->Usb2OverCurrentPin[i] = 0xff;
 382
 383                 if (config->usb2_ports[i].type_c)
 384                         params->PortResetMessageEnable[i] = 1;
 385         }
 386
 387         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 388                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 389                 if (config->usb3_ports[i].enable) {
 390                         params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 391                 } else {
 392                         params->Usb3OverCurrentPin[i] = 0xff;
 393                 }
 394                 if (config->usb3_ports[i].tx_de_emp) {
 395                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 396                         params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 397                 }
 398                 if (config->usb3_ports[i].tx_downscale_amp) {
 399                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 400                         params->Usb3HsioTxDownscaleAmp[i] =
 401                                 config->usb3_ports[i].tx_downscale_amp;
 402                 }
 403         }
 404
 405         /* RP Configs */
 406         for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 407                 params->PcieRpL1Substates[i] =
 408                         get_l1_substate_control(config->PcieRpL1Substates[i]);
 409                 params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
 410                 params->PcieRpAdvancedErrorReporting[i] =
 411                         config->PcieRpAdvancedErrorReporting[i];
 412                 params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
 413                 params->PciePtm[i] = config->PciePtm[i];
 414                 params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i];
 415         }
 416
 417         /* Enable ClkReqDetect for enabled port */
 418         memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
 419                 sizeof(config->PcieRpClkReqDetect));
 420
 421         for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
 422                 if (config->tcss_ports[i].enable)
 423                         params->CpuUsb3OverCurrentPin[i] =
 424                                         config->tcss_ports[i].ocpin;
 425         }
 426
 427         params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
 428
 429         /* PCH UART selection for FSP Debug */
 430         params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 431         ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
 432         params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
 433
 434         /* SATA */
 435         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 436         if (params->SataEnable) {
 437                 params->SataMode = config->SataMode;
 438                 params->SataSalpSupport = config->SataSalpSupport;
 439                 memcpy(params->SataPortsEnable, config->SataPortsEnable,
 440                         sizeof(params->SataPortsEnable));
 441                 memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
 442                         sizeof(params->SataPortsDevSlp));
 443         }
 444
 445         /* S0iX: Selectively enable individual sub-states,
 446          * by default all are enabled.
 447          *
 448          * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
 449          * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
 450          */
 451         params->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(config);
 452
 453         /*
 454          * Power Optimizer for DMI and SATA.
 455          * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.
 456          * Boards not needing the optimizers explicitly disables them by setting
 457          * these disable variables to 1 in devicetree overrides.
 458          */
 459         params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
 460         params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 461
 462         /*
 463          *  Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
 464          *  SataPortsDmVal is the DITO multiplier. Default is 15.
 465          *  SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
 466          *  The default values can be changed from devicetree.
 467          */
 468         for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
 469                 if (config->SataPortsEnableDitoConfig[i]) {
 470                         if (config->SataPortsDmVal[i])
 471                                 params->SataPortsDmVal[i] = config->SataPortsDmVal[i];
 472                         else
 473                                 params->SataPortsDmVal[i] = DEF_DMVAL;
 474
 475                         if (config->SataPortsDitoVal[i])
 476                                 params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
 477                         else
 478                                 params->SataPortsDitoVal[i] = DEF_DITOVAL;
 479                 }
 480         }
 481
 482         params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
 483         params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable;
 484         params->SlowSlewRate[0] = config->SlowSlewRate;
 485
 486         /* Enable TCPU for processor thermal control */
 487         params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
 488
 489         /* Set TccActivationOffset */
 490         params->TccActivationOffset = config->tcc_offset;
 491
 492         /* LAN */
 493         params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 494
 495         /* CNVi */
 496         params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
 497         params->CnviBtCore = config->CnviBtCore;
 498         params->CnviBtAudioOffload = config->CnviBtAudioOffload;
 499         /* Assert if CNVi BT is enabled without CNVi being enabled. */
 500         assert(params->CnviMode || !params->CnviBtCore);
 501         /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
 502         assert(params->CnviBtCore || !params->CnviBtAudioOffload);
 503
 504         /* VMD */
 505         params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
 506
 507         /* THC */
 508         params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
 509         params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
 510
 511         /* Legacy 8254 timer support */
 512         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 513         params->Enable8254ClockGating = !use_8254;
 514         params->Enable8254ClockGatingOnS3 = !use_8254;
 515
 516         /*
 517          * Legacy PM ACPI Timer (and TCO Timer)
 518          * This *must* be 1 in any case to keep FSP from
 519          *  1) enabling PM ACPI Timer emulation in uCode.
 520          *  2) disabling the PM ACPI Timer.
 521          * We handle both by ourself!
 522          */
 523         params->EnableTcoTimer = 1;
 524
 525         /* Enable Hybrid storage auto detection */
 526         if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
 527                 && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) {
 528                 /*
 529                  * CSE Lite SKU does not support hybrid storage dynamic configuration
 530                  * in CSE RO boot, and FSP does not allow to send the strap override
 531                  * HECI commands if CSE is not in normal mode; hence, hybrid storage
 532                  * mode is disabled on CSE RO boot in recovery boot mode.
 533                  */
 534                 printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n");
 535                 params->HybridStorageMode = 0;
 536         } else {
 537                 params->HybridStorageMode = config->HybridStorageMode;
 538         }
 539
 540         /* USB4/TBT */
 541         for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
 542                 dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
 543                 params->ITbtPcieRootPortEn[i] = is_dev_enabled(dev);
 544         }
 545
 546         /* PCH FIVR settings override */
 547         if (config->ext_fivr_settings.configure_ext_fivr) {
 548                 params->PchFivrExtV1p05RailEnabledStates =
 549                         config->ext_fivr_settings.v1p05_enable_bitmap;
 550
 551                 params->PchFivrExtV1p05RailSupportedVoltageStates =
 552                         config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
 553
 554                 params->PchFivrExtVnnRailEnabledStates =
 555                         config->ext_fivr_settings.vnn_enable_bitmap;
 556
 557                 params->PchFivrExtVnnRailSupportedVoltageStates =
 558                         config->ext_fivr_settings.vnn_supported_voltage_bitmap;
 559
 560                 /* convert mV to number of 2.5 mV increments */
 561                 params->PchFivrExtVnnRailSxVoltage =
 562                         (config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25;
 563
 564                 params->PchFivrExtV1p05RailIccMaximum =
 565                         config->ext_fivr_settings.v1p05_icc_max_ma;
 566         }
 567
 568         /* Apply minimum assertion width settings if non-zero */
 569         if (config->PchPmSlpS3MinAssert)
 570                 params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
 571         if (config->PchPmSlpS4MinAssert)
 572                 params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
 573         if (config->PchPmSlpSusMinAssert)
 574                 params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
 575         if (config->PchPmSlpAMinAssert)
 576                 params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
 577
 578         /* Set Power Cycle Duration */
 579         if (config->PchPmPwrCycDur)
 580                 params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
 581                                 config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
 582                                 config->PchPmPwrCycDur);
 583
 584         /* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */
 585         params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
 586
 587         /* Disable C1 C-state Demotion */
 588         params->C1StateAutoDemotion = 0;
 589
 590         /* USB2 Phy Sus power gating setting override */
 591         params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
 592
 593         /*
 594          * Prevent FSP from programming write-once subsystem IDs by providing
 595          * a custom SSID table. Must have at least one entry for the FSP to
 596          * use the table.
 597          */
 598         struct svid_ssid_init_entry {
 599                 union {
 600                         struct {
 601                                 uint64_t reg:12;        /* Register offset */
 602                                 uint64_t function:3;
 603                                 uint64_t device:5;
 604                                 uint64_t bus:8;
 605                                 uint64_t :4;
 606                                 uint64_t segment:16;
 607                                 uint64_t :16;
 608                         };
 609                         uint64_t segbusdevfuncregister;
 610                 };
 611                 struct {
 612                         uint16_t svid;
 613                         uint16_t ssid;
 614                 };
 615                 uint32_t reserved;
 616         };
 617
 618         /*
 619          * The xHCI and HDA devices have RW/L rather than RW/O registers for
 620          * subsystem IDs and so must be written before FspSiliconInit locks
 621          * them with their default values.
 622          */
 623         const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA };
 624         static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)];
 625
 626         for (i = 0; i < ARRAY_SIZE(devfn_table); i++) {
 627                 ssid_table[i].reg       = PCI_SUBSYSTEM_VENDOR_ID;
 628                 ssid_table[i].device    = PCI_SLOT(devfn_table[i]);
 629                 ssid_table[i].function  = PCI_FUNC(devfn_table[i]);
 630                 dev = pcidev_path_on_root(devfn_table[i]);
 631                 if (dev) {
 632                         ssid_table[i].svid = dev->subsystem_vendor;
 633                         ssid_table[i].ssid = dev->subsystem_device;
 634                 }
 635         }
 636
 637         params->SiSsidTablePtr = (uintptr_t)ssid_table;
 638         params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
 639
 640         /*
 641          * Replace the default SVID:SSID value with the values specified in
 642          * the devicetree for the root device.
 643          */
 644         dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 645         params->SiCustomizedSvid = dev->subsystem_vendor;
 646         params->SiCustomizedSsid = dev->subsystem_device;
 647
 648         /* Ensure FSP will program the registers */
 649         params->SiSkipSsidProgramming = 0;
 650
 651         mainboard_silicon_init_params(params);
 652 }
 653
 654 /*
 655  * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
 656  * This platform supports below MultiPhaseSIInit Phase(s):
 657  * Phase   |  FSP return point                                |  Purpose
 658  * ------- + ------------------------------------------------ + -------------------------------
 659  *   1     |  After TCSS initialization completed             |  for TCSS specific init
 660  */
 661 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 662 {
 663         switch (phase_index) {
 664         case 1:
 665                 /* TCSS specific initialization here */
 666                 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
 667                         __FILE__, __func__);
 668
 669                 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
 670                         const config_t *config = config_of_soc();
 671                         tcss_configure(config->typec_aux_bias_pads);
 672                 }
 673                 break;
 674         default:
 675                 break;
 676         }
 677 }
 678
 679 /* Mainboard GPIO Configuration */
 680 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 681 {
 682         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 683 }