src/soc/intel/tigerlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
   5  * Document number: 575857
   6  * Chapter number: 4
   7  */
   8
   9 #include <acpi/acpigen.h>
  10 #include <console/console.h>
  11 #include <device/mmio.h>
  12 #include <device/device.h>
  13 #include <drivers/intel/pmc_mux/chip.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/pmc.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/pmc_ipc.h>
  18 #include <intelblocks/rtc.h>
  19 #include <soc/lpm.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pm.h>
  22 #include <soc/soc_chip.h>
  23 #include <bootstate.h>
  24
  25 #define PMC_HID         "INTC1026"
  26
  27 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  28 {
  29         uint32_t reg;
  30         uint8_t *pmcbase = pmc_mmio_regs();
  31
  32         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  33                 enable ? "En" : "Dis", sx + '0');
  34         reg = read32(pmcbase + offset);
  35         if (enable)
  36                 reg |= mask;
  37         else
  38                 reg &= ~mask;
  39         write32(pmcbase + offset, reg);
  40 }
  41
  42 static void config_deep_s5(int on_ac, int on_dc)
  43 {
  44         /* Treat S4 the same as S5. */
  45         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  46         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  47         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  48         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  49 }
  50
  51 static void config_deep_s3(int on_ac, int on_dc)
  52 {
  53         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  54         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  55 }
  56
  57 static void config_deep_sx(uint32_t deepsx_config)
  58 {
  59         uint32_t reg;
  60         uint8_t *pmcbase = pmc_mmio_regs();
  61
  62         reg = read32(pmcbase + DSX_CFG);
  63         reg &= ~DSX_CFG_MASK;
  64         reg |= deepsx_config;
  65         write32(pmcbase + DSX_CFG, reg);
  66 }
  67
  68 static void soc_pmc_enable(struct device *dev)
  69 {
  70         const config_t *config = config_of_soc();
  71
  72         rtc_init();
  73
  74         pmc_set_power_failure_state(true);
  75         pmc_gpe_init();
  76
  77         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  78         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  79         config_deep_sx(config->deep_sx_config);
  80 }
  81
  82 static void soc_pmc_read_resources(struct device *dev)
  83 {
  84         struct resource *res;
  85
  86         /* Add the fixed MMIO resource */
  87         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  88
  89         /* Add the fixed I/O resource */
  90         res = new_resource(dev, 1);
  91         res->base = (resource_t)ACPI_BASE_ADDRESS;
  92         res->size = (resource_t)ACPI_BASE_SIZE;
  93         res->limit = res->base + res->size - 1;
  94         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  95 }
  96
  97 static void soc_pmc_fill_ssdt(const struct device *dev)
  98 {
  99         const char *scope = acpi_device_scope(dev);
 100         const char *name = acpi_device_name(dev);
 101         if (!scope || !name)
 102                 return;
 103
 104         acpigen_write_scope(scope);
 105         acpigen_write_device(name);
 106
 107         acpigen_write_name_string("_HID", PMC_HID);
 108         acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller");
 109         acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 110
 111         /*
 112          * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
 113          * The PMC gets 0xFE000000 - 0xFE00FFFF.
 114          */
 115         acpigen_write_name("_CRS");
 116         acpigen_write_resourcetemplate_header();
 117         acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
 118         acpigen_write_resourcetemplate_footer();
 119
 120         /* Define IPC Write Method */
 121         if (CONFIG(PMC_IPC_ACPI_INTERFACE))
 122                 pmc_ipc_acpi_fill_ssdt();
 123
 124         acpigen_pop_len(); /* PMC Device */
 125         acpigen_pop_len(); /* Scope */
 126
 127         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
 128                 const struct soc_pmc_lpm tgl_pmc_lpm = {
 129                         .num_substates = 8,
 130                         .num_req_regs = 6,
 131                         .lpm_ipc_offset = 0x1000,
 132                         .req_reg_stride = 0x30,
 133                         .lpm_enable_mask = get_supported_lpm_mask(config_of_soc()),
 134                 };
 135
 136                 generate_acpi_power_engine_with_lpm(&tgl_pmc_lpm);
 137         }
 138
 139         printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
 140                dev_path(dev));
 141 }
 142
 143 static void soc_pmc_init(struct device *dev)
 144 {
 145         /*
 146          * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
 147          * to ensure the ordering does not break the assumptions that other
 148          * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
 149          * ACPI mode, other drivers may take different actions based on this
 150          * (e.g. Chrome EC will flush any pending hostevent bits). Because
 151          * TGL has its PMC device available for device_operations, it can be
 152          * done from the "ops->init" callback.
 153          */
 154         pmc_set_acpi_mode();
 155
 156         /*
 157          * Disable ACPI PM timer based on Kconfig
 158          *
 159          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 160          * Disabling ACPI PM timer also switches off TCO
 161          */
 162         if (!CONFIG(USE_PM_ACPI_TIMER))
 163                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 164 }
 165
 166 static void pm1_enable_pwrbtn_smi(void *unused)
 167 {
 168         /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
 169         pmc_update_pm1_enable(PWRBTN_EN);
 170 }
 171
 172 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 173
 174 /*
 175  * `pmc_final` function is native implementation of equivalent events performed by
 176  * each FSP NotifyPhase() API invocations.
 177  *
 178  *
 179  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 180  *
 181  * Perform the PMCON status bit clear operation from `.final`
 182  * to cover any such chances where later boot stage requested a global
 183  * reset and PMCON status bit remains set.
 184  */
 185 static void pmc_final(struct device *dev)
 186 {
 187         pmc_clear_pmcon_sts();
 188 }
 189
 190 struct device_operations pmc_ops = {
 191         .read_resources   = soc_pmc_read_resources,
 192         .set_resources    = noop_set_resources,
 193         .init             = soc_pmc_init,
 194         .enable           = soc_pmc_enable,
 195 #if CONFIG(HAVE_ACPI_TABLES)
 196         .acpi_fill_ssdt   = soc_pmc_fill_ssdt,
 197 #endif
 198         .scan_bus         = scan_static_bus,
 199         .final            = pmc_final,
 200 };