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soc/intel: Remove blank lines before '}' and after '{'
[coreboot2.git] / src / soc / intel / xeon_sp / spr / hob_display.c
blob582413cdfea50ee8b6d9a6ec372c71910c3a319a
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <fsp/util.h>
5 #include <hob_cxlnode.h>
6 #include <hob_iiouds.h>
7 #include <hob_memmap.h>
8 #include <lib.h>
9 #include <soc/soc_util.h>
10
11 static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
12 static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
13 static const uint8_t fsp_hob_cxlnode_guid[16] = FSP_HOB_CXLNODE_GUID;
14
15 struct guid_name_map {
16 const void *guid;
17 const char *name;
18 };
19
20 static const struct guid_name_map guid_names[] = {
21 {fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID"},
22 {fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID"},
23 {fsp_hob_cxlnode_guid, "FSP_HOB_CXLNODE_GUID"},
24 };
25
26 const char *soc_get_guid_name(const uint8_t *guid)
27 {
28 size_t index;
29
30 /* Compare the GUID values in this module */
31 for (index = 0; index < ARRAY_SIZE(guid_names); index++)
32 if (fsp_guid_compare(guid, guid_names[index].guid))
33 return guid_names[index].name;
34
35 return NULL;
36 }
37
38 void soc_display_memmap_hob(const struct SystemMemoryMapHob **hob_addr)
39 {
40 struct SystemMemoryMapHob *hob = (struct SystemMemoryMapHob *)*hob_addr;
41
42 printk(BIOS_DEBUG, "================== MEMORY MAP HOB DATA ==================\n");
43 printk(BIOS_DEBUG, "hob: %p, structure size: 0x%lx\n", hob, sizeof(*hob));
44
45 printk(BIOS_DEBUG,
46 "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, "
47 "highMemSize: 0x%x\n",
48 hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize);
49 printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n", hob->memSize, hob->memFreq);
50
51 printk(BIOS_DEBUG, "\tNumChPerMC: %d\n", hob->NumChPerMC);
52 printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d, entry size: %ld\n",
53 hob->numberEntries, sizeof(SYSTEM_MEMORY_MAP_ELEMENT));
54
55 for (int e = 0; e < hob->numberEntries; ++e) {
56 const struct SystemMemoryMapElement *mem_element = &hob->Element[e];
57 printk(BIOS_DEBUG,
58 "\t\tmemory_map %d, SocketId: 0x%x, BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n",
59 e, mem_element->SocketId, mem_element->BaseAddress,
60 mem_element->ElementSize, mem_element->Type);
61 }
62
63 printk(BIOS_DEBUG,
64 "^^^ MEMMAP_SOCKET: %ld, ChannelDevice: %ld, MEMMAP_DIMM_DEVICE_INFO_STRUCT: %ld\n",
65 sizeof(MEMMAP_SOCKET), sizeof(struct ChannelDevice),
66 sizeof(MEMMAP_DIMM_DEVICE_INFO_STRUCT));
67 printk(BIOS_DEBUG, "^^^ Element Offset: %ld\n",
68 offsetof(SYSTEM_MEMORY_MAP_HOB, Element));
69 printk(BIOS_DEBUG, "^^^ Socket Offset: %ld\n",
70 offsetof(SYSTEM_MEMORY_MAP_HOB, Socket));
71 printk(BIOS_DEBUG, "^^^ ChannelInfo Offset: %ld\n",
72 offsetof(MEMMAP_SOCKET, ChannelInfo));
73 printk(BIOS_DEBUG, "^^^ DimmInfo Offset: %ld\n",
74 offsetof(struct ChannelDevice, DimmInfo));
75 printk(BIOS_DEBUG, "^^^ DimmSize Offset: %ld\n",
76 offsetof(struct DimmDevice, DimmSize));
77
78 for (int s = 0; s < MAX_SOCKET; ++s) {
79 if (!hob->Socket[s].SocketEnabled)
80 continue;
81 for (int ch = 0; ch < MAX_CH; ++ch) {
82 if (!hob->Socket[s].ChannelInfo[ch].Enabled)
83 continue;
84 for (int dimm = 0; dimm < MAX_DIMM; ++dimm) {
85 if (!hob->Socket[s].ChannelInfo[ch].DimmInfo[dimm].Present)
86 continue;
87 printk(BIOS_DEBUG,
88 "\tsocket: %d, ch: %d, dimm: %d, enabled: %d, DimmSize: 0x%x\n",
89 s, ch, dimm,
90 hob->Socket[s].ChannelInfo[ch].DimmInfo[dimm].Enabled,
91 hob->Socket[s].ChannelInfo[ch].DimmInfo[dimm].DimmSize);
92 }
93 }
94 }
95
96 printk(BIOS_DEBUG, "\tBiosFisVersion: 0x%x\n", hob->BiosFisVersion);
97 printk(BIOS_DEBUG, "\tMmiohBase: 0x%x\n", hob->MmiohBase);
98
99 hexdump(hob, sizeof(*hob));
100 }
101
102 void soc_display_iio_universal_data_hob(const IIO_UDS *hob)
103 {
104 printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n");
105 printk(BIOS_DEBUG, "hob: %p, structure size: 0x%lx\n", hob, sizeof(*hob));
106
107 printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n");
108 printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus);
109 printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit);
110
111 printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
112 printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
113 printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
114 printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
115 hob->PlatformData.PlatGlobalMmio32Base);
116 printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
117 hob->PlatformData.PlatGlobalMmio32Limit);
118 printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
119 hob->PlatformData.PlatGlobalMmio64Base);
120 printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
121 hob->PlatformData.PlatGlobalMmio64Limit);
122 printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
123 printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
124 printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize);
125 printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm);
126 printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO);
127 printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber);
128 printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity);
129 printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity);
130 printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n",
131 hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo);
132
133 for (uint8_t s = 0; s < MAX_SOCKET; ++s) {
134 printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s);
135 printk(BIOS_DEBUG, "\tValid: 0x%x\n", hob->PlatformData.IIO_resource[s].Valid);
136 printk(BIOS_DEBUG, "\tSocketID: 0x%x\n",
137 hob->PlatformData.IIO_resource[s].SocketID);
138 printk(BIOS_DEBUG, "\tBusBase: 0x%x\n",
139 hob->PlatformData.IIO_resource[s].BusBase);
140 printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n",
141 hob->PlatformData.IIO_resource[s].BusLimit);
142 printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n",
143 hob->PlatformData.IIO_resource[s].PciResourceIoBase);
144 printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n",
145 hob->PlatformData.IIO_resource[s].PciResourceIoLimit);
146 printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n",
147 hob->PlatformData.IIO_resource[s].IoApicBase);
148 printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
149 hob->PlatformData.IIO_resource[s].IoApicLimit);
150 printk(BIOS_DEBUG, "\tMmio32Base: 0x%x\n",
151 hob->PlatformData.IIO_resource[s].Mmio32Base);
152 printk(BIOS_DEBUG, "\tMmio32Limit: 0x%x\n",
153 hob->PlatformData.IIO_resource[s].Mmio32Limit);
154 printk(BIOS_DEBUG, "\tMmio64Base: 0x%llx\n",
155 hob->PlatformData.IIO_resource[s].Mmio64Base);
156 printk(BIOS_DEBUG, "\tMmio64Limit: 0x%llx\n",
157 hob->PlatformData.IIO_resource[s].Mmio64Limit);
158
159 printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
160 for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
161 const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
162 printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x);
163 printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality);
164 printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
165 printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
166 printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase);
167 printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit);
168 printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
169 ri->PciResourceIoBase);
170 printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
171 ri->PciResourceIoLimit);
172 printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
173 printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
174 printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base);
175 printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit);
176 printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
177 ri->PciResourceMem32Base);
178 printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",
179 ri->PciResourceMem32Limit);
180 printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base);
181 printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit);
182 printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n",
183 ri->PciResourceMem64Base);
184 printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n",
185 ri->PciResourceMem64Limit);
186 printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress);
187 }
188
189 printk(BIOS_DEBUG, "\t============ PcieInfo ================\n");
190 IIO_RESOURCE_INSTANCE iio_resource = hob->PlatformData.IIO_resource[s];
191 for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
192 printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", p,
193 iio_resource.PcieInfo.PortInfo[p].Device,
194 iio_resource.PcieInfo.PortInfo[p].Function);
195 }
196 }
197
198 hexdump(hob, sizeof(*hob));
199 }
200
201 static void soc_display_cxlnode_hob(const CXL_NODE_SOCKET *hob)
202 {
203 printk(BIOS_DEBUG, "===================== CXLNODE HOB DATA =====================\n");
204 printk(BIOS_DEBUG, "hob: %p, structure size: 0x%lx\n", hob, sizeof(*hob) * MAX_SOCKET);
205
206 for (uint8_t skt_id = 0; skt_id < MAX_SOCKET; skt_id++) {
207 printk(BIOS_DEBUG, "\tSocket:%d, CxlNodeCount: 0x%x\n", skt_id,
208 hob[skt_id].CxlNodeCount);
209 for (uint8_t i = 0; i < hob[skt_id].CxlNodeCount; ++i) {
210 printk(BIOS_DEBUG, "\tCxlNodeInfo[%d]:\n", i);
211 const CXL_NODE_INFO node = hob[skt_id].CxlNodeInfo[i];
212 printk(BIOS_DEBUG, "\t\tSerialNumber: 0x%llx\n", node.SerialNumber);
213 printk(BIOS_DEBUG, "\t\tVendorId: 0x%x\n", node.VendorId);
214 printk(BIOS_DEBUG, "\t\tAttr: 0x%x\n", node.Attr);
215 printk(BIOS_DEBUG, "\t\tAddress: 0x%x\n", node.Address);
216 printk(BIOS_DEBUG, "\t\tSize: 0x%x\n", node.Size);
217 printk(BIOS_DEBUG, "\t\tWays: 0x%x\n", node.Ways);
218 printk(BIOS_DEBUG, "\t\tSocketBitmap: 0x%x\n", node.SocketBitmap);
219 printk(BIOS_DEBUG,
220 "\t\tPerfData format: RdLatency(0.1ns), WrLatency(0.1ns), RdBW(100MB/s), WrBW(100MB/s)\n");
221 printk(BIOS_DEBUG,
222 "\t\tEfiMemType and PerfData are invalid for SPR-SP.\n");
223 }
224 }
225
226 hexdump(hob, sizeof(*hob) * MAX_SOCKET);
227 }
228
229 void soc_display_hob(const struct hob_header *hob)
230 {
231 uint8_t *guid;
232
233 if (hob->type != HOB_TYPE_GUID_EXTENSION)
234 return;
235
236 guid = (uint8_t *)fsp_hob_header_to_resource(hob);
237
238 if (fsp_guid_compare(guid, fsp_hob_iio_uds_guid))
239 soc_display_iio_universal_data_hob((const IIO_UDS *)(guid + 16));
240 else if (fsp_guid_compare(guid, fsp_hob_memmap_guid))
241 soc_display_memmap_hob((const struct SystemMemoryMapHob **)(guid + 16));
242 else if (fsp_guid_compare(guid, fsp_hob_cxlnode_guid))
243 soc_display_cxlnode_hob((const CXL_NODE_SOCKET *)(guid + 16));
244 }
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