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HEAD
mb/google/brya: Create rull variant
[coreboot2.git]
/
src
/
drivers
/
amd
/
agesa
/
exit_car.S
blob
894bf4030f3a767786efef21817def80bf2608d8
1
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gcccar.inc>
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#include <cpu/x86/cache.h>
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.code32
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.globl chipset_teardown_car
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chipset_teardown_car:
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pop %esp
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/* Disable cache */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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AMD_DISABLE_STACK
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/* enable cache */
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movl %cr0, %eax
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andl $(~(CR0_CD | CR0_NW)), %eax
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movl %eax, %cr0
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jmp *%esp