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mb/google/brya: Create rull variant
[coreboot2.git] / src / drivers / i2c / designware / dw_i2c.c
blob3bcb51ab6c22b19d3db3805a9034f2e3305f23d4
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpigen.h>
4 #include <device/mmio.h>
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/i2c_bus.h>
8 #include <device/i2c_simple.h>
9 #include <string.h>
10 #include <timer.h>
11 #include <types.h>
12 #include "dw_i2c.h"
13
14 /* Use a ~10ms timeout for various operations */
15 #define DW_I2C_TIMEOUT_US 10000
16 /* Timeout for waiting for FIFO to flush */
17 #define DW_I2C_FLUSH_TIMEOUT_US 160000
18
19 /* High and low times in different speed modes (in ns) */
20 enum {
21 /* SDA Hold Time */
22 DEFAULT_SDA_HOLD_TIME = 300,
23 /* Standard Speed */
24 MIN_SS_SCL_HIGHTIME = 4000,
25 MIN_SS_SCL_LOWTIME = 4700,
26 /* Fast Speed */
27 MIN_FS_SCL_HIGHTIME = 600,
28 MIN_FS_SCL_LOWTIME = 1300,
29 /* Fast Plus Speed */
30 MIN_FP_SCL_HIGHTIME = 260,
31 MIN_FP_SCL_LOWTIME = 500,
32 /* High Speed */
33 MIN_HS_SCL_HIGHTIME = 60,
34 MIN_HS_SCL_LOWTIME = 160,
35 };
36
37 /* Frequency represented as ticks per ns. Can also be used to calculate
38 * the number of ticks to meet a time target or the period. */
39 struct freq {
40 uint32_t ticks;
41 uint32_t ns;
42 };
43
44 /* Control register definitions */
45 enum {
46 CONTROL_MASTER_MODE = (1 << 0),
47 CONTROL_SPEED_SS = (1 << 1),
48 CONTROL_SPEED_FS = (2 << 1),
49 CONTROL_SPEED_HS = (3 << 1),
50 CONTROL_SPEED_MASK = (3 << 1),
51 CONTROL_10BIT_SLAVE = (1 << 3),
52 CONTROL_10BIT_MASTER = (1 << 4),
53 CONTROL_RESTART_ENABLE = (1 << 5),
54 CONTROL_SLAVE_DISABLE = (1 << 6),
55 };
56
57 /* Command/Data register definitions */
58 enum {
59 CMD_DATA_CMD = (1 << 8),
60 CMD_DATA_STOP = (1 << 9),
61 };
62
63 /* Status register definitions */
64 enum {
65 STATUS_ACTIVITY = (1 << 0),
66 STATUS_TX_FIFO_NOT_FULL = (1 << 1),
67 STATUS_TX_FIFO_EMPTY = (1 << 2),
68 STATUS_RX_FIFO_NOT_EMPTY = (1 << 3),
69 STATUS_RX_FIFO_FULL = (1 << 4),
70 STATUS_MASTER_ACTIVITY = (1 << 5),
71 STATUS_SLAVE_ACTIVITY = (1 << 6),
72 };
73
74 /* Enable register definitions */
75 enum {
76 ENABLE_CONTROLLER = (1 << 0),
77 };
78
79 /* Interrupt status register definitions */
80 enum {
81 INTR_STAT_RX_UNDER = (1 << 0),
82 INTR_STAT_RX_OVER = (1 << 1),
83 INTR_STAT_RX_FULL = (1 << 2),
84 INTR_STAT_TX_OVER = (1 << 3),
85 INTR_STAT_TX_EMPTY = (1 << 4),
86 INTR_STAT_RD_REQ = (1 << 5),
87 INTR_STAT_TX_ABORT = (1 << 6),
88 INTR_STAT_RX_DONE = (1 << 7),
89 INTR_STAT_ACTIVITY = (1 << 8),
90 INTR_STAT_STOP_DET = (1 << 9),
91 INTR_STAT_START_DET = (1 << 10),
92 INTR_STAT_GEN_CALL = (1 << 11),
93 };
94
95 /* I2C Controller MMIO register space */
96 struct dw_i2c_regs {
97 uint32_t control; /* 0x0 */
98 uint32_t target_addr; /* 0x4 */
99 uint32_t slave_addr; /* 0x8 */
100 uint32_t master_addr; /* 0xc */
101 uint32_t cmd_data; /* 0x10 */
102 uint32_t ss_scl_hcnt; /* 0x14 */
103 uint32_t ss_scl_lcnt; /* 0x18 */
104 uint32_t fs_scl_hcnt; /* 0x1c */
105 uint32_t fs_scl_lcnt; /* 0x20 */
106 uint32_t hs_scl_hcnt; /* 0x24 */
107 uint32_t hs_scl_lcnt; /* 0x28 */
108 uint32_t intr_stat; /* 0x2c */
109 uint32_t intr_mask; /* 0x30 */
110 uint32_t raw_intr_stat; /* 0x34 */
111 uint32_t rx_thresh; /* 0x38 */
112 uint32_t tx_thresh; /* 0x3c */
113 uint32_t clear_intr; /* 0x40 */
114 uint32_t clear_rx_under_intr; /* 0x44 */
115 uint32_t clear_rx_over_intr; /* 0x48 */
116 uint32_t clear_tx_over_intr; /* 0x4c */
117 uint32_t clear_rd_req_intr; /* 0x50 */
118 uint32_t clear_tx_abrt_intr; /* 0x54 */
119 uint32_t clear_rx_done_intr; /* 0x58 */
120 uint32_t clear_activity_intr; /* 0x5c */
121 uint32_t clear_stop_det_intr; /* 0x60 */
122 uint32_t clear_start_det_intr; /* 0x64 */
123 uint32_t clear_gen_call_intr; /* 0x68 */
124 uint32_t enable; /* 0x6c */
125 uint32_t status; /* 0x70 */
126 uint32_t tx_level; /* 0x74 */
127 uint32_t rx_level; /* 0x78 */
128 uint32_t sda_hold; /* 0x7c */
129 uint32_t tx_abort_source; /* 0x80 */
130 uint32_t slv_data_nak_only; /* 0x84 */
131 uint32_t dma_cr; /* 0x88 */
132 uint32_t dma_tdlr; /* 0x8c */
133 uint32_t dma_rdlr; /* 0x90 */
134 uint32_t sda_setup; /* 0x94 */
135 uint32_t ack_general_call; /* 0x98 */
136 uint32_t enable_status; /* 0x9c */
137 uint32_t fs_spklen; /* 0xa0 */
138 uint32_t hs_spklen; /* 0xa4 */
139 uint32_t clr_restart_det; /* 0xa8 */
140 uint32_t reserved[18]; /* 0xac - 0xf0 */
141 uint32_t comp_param1; /* 0xf4 */
142 uint32_t comp_version; /* 0xf8 */
143 uint32_t comp_type; /* 0xfc */
144 } __packed;
145
146 /* Constant value defined in the DesignWare DW_apb_i2c Databook. */
147 #define DW_I2C_COMP_TYPE 0x44570140
148
149 static const struct i2c_descriptor {
150 enum i2c_speed speed;
151 struct freq freq;
152 int min_thigh_ns;
153 int min_tlow_ns;
154 } speed_descriptors[] = {
155 {
156 .speed = I2C_SPEED_STANDARD,
157 .freq = {
158 .ticks = 100,
159 .ns = 1000*1000,
160 },
161 .min_thigh_ns = MIN_SS_SCL_HIGHTIME,
162 .min_tlow_ns = MIN_SS_SCL_LOWTIME,
163 },
164 {
165 .speed = I2C_SPEED_FAST,
166 .freq = {
167 .ticks = 400,
168 .ns = 1000*1000,
169 },
170 .min_thigh_ns = MIN_FS_SCL_HIGHTIME,
171 .min_tlow_ns = MIN_FS_SCL_LOWTIME,
172 },
173 {
174 .speed = I2C_SPEED_FAST_PLUS,
175 .freq = {
176 .ticks = 1,
177 .ns = 1000,
178 },
179 .min_thigh_ns = MIN_FP_SCL_HIGHTIME,
180 .min_tlow_ns = MIN_FP_SCL_LOWTIME,
181 },
182 {
183 /* 100pF max capacitance */
184 .speed = I2C_SPEED_HIGH,
185 .freq = {
186 .ticks = 3400,
187 .ns = 1000*1000,
188 },
189 .min_thigh_ns = MIN_HS_SCL_HIGHTIME,
190 .min_tlow_ns = MIN_HS_SCL_LOWTIME,
191 },
192 };
193
194 static const struct soc_clock {
195 int clk_speed_mhz;
196 struct freq freq;
197 } soc_clocks[] = {
198 {
199 .clk_speed_mhz = 100,
200 .freq = {
201 .ticks = 100,
202 .ns = 1000,
203 },
204 },
205 {
206 .clk_speed_mhz = 120,
207 .freq = {
208 .ticks = 120,
209 .ns = 1000,
210 },
211 },
212 {
213 .clk_speed_mhz = 133,
214 .freq = {
215 .ticks = 400,
216 .ns = 3000,
217 },
218 },
219 {
220 .clk_speed_mhz = 150,
221 .freq = {
222 .ticks = 600,
223 .ns = 4000,
224 },
225 },
226 {
227 .clk_speed_mhz = 216,
228 .freq = {
229 .ticks = 1080,
230 .ns = 5000,
231 },
232 },
233 };
234
235 static const struct i2c_descriptor *get_bus_descriptor(enum i2c_speed speed)
236 {
237 size_t i;
238
239 for (i = 0; i < ARRAY_SIZE(speed_descriptors); i++)
240 if (speed == speed_descriptors[i].speed)
241 return &speed_descriptors[i];
242
243 return NULL;
244 }
245
246 static const struct soc_clock *get_soc_descriptor(int ic_clk)
247 {
248 size_t i;
249
250 for (i = 0; i < ARRAY_SIZE(soc_clocks); i++)
251 if (ic_clk == soc_clocks[i].clk_speed_mhz)
252 return &soc_clocks[i];
253
254 return NULL;
255 }
256
257 static int counts_from_time(const struct freq *f, int ns)
258 {
259 return DIV_ROUND_UP(f->ticks * ns, f->ns);
260 }
261
262 static int counts_from_freq(const struct freq *fast, const struct freq *slow)
263 {
264 return DIV_ROUND_UP(fast->ticks * slow->ns, fast->ns * slow->ticks);
265 }
266
267 /* Enable this I2C controller */
268 static void dw_i2c_enable(struct dw_i2c_regs *regs)
269 {
270 uint32_t enable = read32(&regs->enable);
271
272 if (!(enable & ENABLE_CONTROLLER))
273 write32(&regs->enable, enable | ENABLE_CONTROLLER);
274 }
275
276 /* Disable this I2C controller */
277 static enum cb_err dw_i2c_disable(struct dw_i2c_regs *regs)
278 {
279 uint32_t enable = read32(&regs->enable);
280
281 if (enable & ENABLE_CONTROLLER) {
282 struct stopwatch sw;
283
284 write32(&regs->enable, enable & ~ENABLE_CONTROLLER);
285
286 /* Wait for enable bit to clear */
287 stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US);
288 while (read32(&regs->enable_status) & ENABLE_CONTROLLER)
289 if (stopwatch_expired(&sw))
290 return CB_ERR;
291 }
292
293 return CB_SUCCESS;
294 }
295
296 /* Wait for this I2C controller to go idle for transmit */
297 static enum cb_err dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs)
298 {
299 struct stopwatch sw;
300
301 /* Start timeout for up to 16 bytes in FIFO */
302 stopwatch_init_usecs_expire(&sw, DW_I2C_FLUSH_TIMEOUT_US);
303
304 while (!stopwatch_expired(&sw)) {
305 uint32_t status = read32(&regs->status);
306
307 /* Check for master activity and keep waiting */
308 if (status & STATUS_MASTER_ACTIVITY)
309 continue;
310
311 /* Check for TX FIFO empty to indicate TX idle */
312 if (status & STATUS_TX_FIFO_EMPTY)
313 return CB_SUCCESS;
314 }
315
316 /* Timed out while waiting for bus to go idle */
317 return CB_ERR;
318 }
319
320 /* Transfer one byte of one segment, sending stop bit if requested */
321 static enum cb_err dw_i2c_transfer_byte(struct dw_i2c_regs *regs,
322 const struct i2c_msg *segment,
323 size_t byte, int send_stop)
324 {
325 struct stopwatch sw;
326 uint32_t cmd = CMD_DATA_CMD; /* Read op */
327
328 stopwatch_init_usecs_expire(&sw, CONFIG_I2C_TRANSFER_TIMEOUT_US);
329
330 if (!(segment->flags & I2C_M_RD)) {
331 /* Write op only: Wait for FIFO not full */
332 while (!(read32(&regs->status) & STATUS_TX_FIFO_NOT_FULL)) {
333 if (stopwatch_expired(&sw)) {
334 printk(BIOS_ERR, "I2C transmit timeout\n");
335 return CB_ERR;
336 }
337 }
338 cmd = segment->buf[byte];
339 }
340
341 /* Send stop on last byte, if desired */
342 if (send_stop && byte == segment->len - 1)
343 cmd |= CMD_DATA_STOP;
344
345 write32(&regs->cmd_data, cmd);
346
347 if (segment->flags & I2C_M_RD) {
348 /* Read op only: Wait for FIFO data and store it */
349 while (!(read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY)) {
350 if (stopwatch_expired(&sw)) {
351 printk(BIOS_ERR, "I2C receive timeout\n");
352 return CB_ERR;
353 }
354 }
355 segment->buf[byte] = read32(&regs->cmd_data);
356 }
357
358 return CB_SUCCESS;
359 }
360
361 static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments,
362 size_t count)
363 {
364 struct stopwatch sw;
365 struct dw_i2c_regs *regs;
366 size_t byte;
367 enum cb_err ret = CB_ERR;
368 bool seg_zero_len = segments->len == 0;
369
370 regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
371 if (!regs) {
372 printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
373 return CB_ERR;
374 }
375
376 /* The assumption is that the host controller is disabled -- either
377 after running this function or from performing the initialization
378 sequence in dw_i2c_init(). */
379
380 /* Set target slave address */
381 write32(&regs->target_addr, segments->slave);
382
383 dw_i2c_enable(regs);
384
385 if (seg_zero_len)
386 /* stop immediately */
387 write32(&regs->cmd_data, CMD_DATA_STOP);
388
389 /* Process each segment */
390 while (count--) {
391 if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) {
392 printk(BIOS_DEBUG, "i2c %u:%02x %s %d bytes : ",
393 bus, segments->slave,
394 (segments->flags & I2C_M_RD) ? "R" : "W",
395 segments->len);
396 }
397
398 /* Read or write each byte in segment */
399 for (byte = 0; byte < segments->len; byte++) {
400 /*
401 * Set stop condition on final segment only.
402 * Repeated start will be automatically generated
403 * by the controller on R->W or W->R switch.
404 */
405 if (dw_i2c_transfer_byte(regs, segments, byte, count == 0) !=
406 CB_SUCCESS) {
407 printk(BIOS_ERR, "I2C %s failed: bus %u "
408 "addr 0x%02x\n",
409 (segments->flags & I2C_M_RD) ?
410 "read" : "write", bus, segments->slave);
411 goto out;
412 }
413 }
414
415 if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) {
416 int j;
417 for (j = 0; j < segments->len; j++)
418 printk(BIOS_DEBUG, "%02x ", segments->buf[j]);
419 printk(BIOS_DEBUG, "\n");
420 }
421
422 segments++;
423 }
424
425 /* Wait for interrupt status to indicate transfer is complete */
426 stopwatch_init_usecs_expire(&sw, CONFIG_I2C_TRANSFER_TIMEOUT_US);
427 while (!(read32(&regs->raw_intr_stat) & INTR_STAT_STOP_DET)) {
428 if (stopwatch_expired(&sw)) {
429 printk(BIOS_ERR, "I2C stop bit not received\n");
430 goto out;
431 }
432 }
433
434 /* Read to clear INTR_STAT_STOP_DET */
435 read32(&regs->clear_stop_det_intr);
436
437 /* Check TX abort */
438 if (read32(&regs->raw_intr_stat) & INTR_STAT_TX_ABORT) {
439 printk(seg_zero_len ? BIOS_SPEW : BIOS_ERR, "I2C TX abort detected (%08x)\n",
440 read32(&regs->tx_abort_source));
441 /* clear INTR_STAT_TX_ABORT */
442 read32(&regs->clear_tx_abrt_intr);
443 goto out;
444 }
445
446 /* Wait for the bus to go idle */
447 if (dw_i2c_wait_for_bus_idle(regs) != CB_SUCCESS) {
448 printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
449 goto out;
450 }
451
452 /* Flush the RX FIFO in case it is not empty */
453 stopwatch_init_usecs_expire(&sw, DW_I2C_FLUSH_TIMEOUT_US);
454 while (read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY) {
455 if (stopwatch_expired(&sw)) {
456 printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n");
457 goto out;
458 }
459 read32(&regs->cmd_data);
460 }
461
462 ret = CB_SUCCESS;
463
464 out:
465 read32(&regs->clear_intr);
466 dw_i2c_disable(regs);
467 return ret;
468 }
469
470 static enum cb_err dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count)
471 {
472 const struct i2c_msg *orig_msg = msg;
473 size_t i;
474 size_t start;
475 uint16_t addr;
476
477 if (count == 0 || !msg)
478 return -1;
479
480 /* Break up the transfers at the differing slave address boundary. */
481 addr = orig_msg->slave;
482
483 for (i = 0, start = 0; i < count; i++, msg++) {
484 if (addr != msg->slave) {
485 if (_dw_i2c_transfer(bus, &orig_msg[start], i - start) != CB_SUCCESS)
486 return CB_ERR;
487 start = i;
488 addr = msg->slave;
489 }
490 }
491
492 return _dw_i2c_transfer(bus, &orig_msg[start], count - start);
493 }
494
495 /* Global I2C bus handler, defined in include/device/i2c_simple.h */
496 int platform_i2c_transfer(unsigned int bus, struct i2c_msg *msg, int count)
497 {
498 return dw_i2c_transfer(bus, msg, count < 0 ? 0 : count) == CB_SUCCESS ? 0 : -1;
499 }
500
501 static enum cb_err dw_i2c_set_speed_config(unsigned int bus,
502 const struct dw_i2c_speed_config *config)
503 {
504 struct dw_i2c_regs *regs;
505 void *hcnt_reg, *lcnt_reg;
506
507 regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
508 if (!regs || !config)
509 return CB_ERR;
510
511 /* Nothing to do if no values are set */
512 if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold)
513 return CB_SUCCESS;
514
515 if (config->speed >= I2C_SPEED_HIGH) {
516 /* High and Fast Ultra speed */
517 hcnt_reg = &regs->hs_scl_hcnt;
518 lcnt_reg = &regs->hs_scl_lcnt;
519 } else if (config->speed >= I2C_SPEED_FAST) {
520 /* Fast and Fast-Plus speed */
521 hcnt_reg = &regs->fs_scl_hcnt;
522 lcnt_reg = &regs->fs_scl_lcnt;
523 } else {
524 /* Standard speed */
525 hcnt_reg = &regs->ss_scl_hcnt;
526 lcnt_reg = &regs->ss_scl_lcnt;
527 }
528
529 /* SCL count must be set after the speed is selected */
530 if (config->scl_hcnt)
531 write32(hcnt_reg, config->scl_hcnt);
532 if (config->scl_lcnt)
533 write32(lcnt_reg, config->scl_lcnt);
534
535 /* Set SDA Hold Time register */
536 if (config->sda_hold)
537 write32(&regs->sda_hold, config->sda_hold);
538
539 return CB_SUCCESS;
540 }
541
542 static enum cb_err dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs,
543 enum i2c_speed speed,
544 const struct dw_i2c_bus_config *bcfg,
545 int ic_clk,
546 struct dw_i2c_speed_config *config)
547 {
548 const struct i2c_descriptor *bus;
549 const struct soc_clock *soc;
550 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt, spk_cnt;
551 int hcnt, lcnt, period_cnt, diff, tot;
552 int data_hold_time_ns;
553
554 bus = get_bus_descriptor(speed);
555 soc = get_soc_descriptor(ic_clk);
556
557 if (bus == NULL) {
558 printk(BIOS_ERR, "dw_i2c: invalid bus speed %d\n", speed);
559 return CB_ERR;
560 }
561
562 if (soc == NULL) {
563 printk(BIOS_ERR, "dw_i2c: invalid SoC clock speed %d MHz\n",
564 ic_clk);
565 return CB_ERR;
566 }
567
568 /* Get the proper spike suppression count based on target speed. */
569 if (speed >= I2C_SPEED_HIGH)
570 spk_cnt = read32(&regs->hs_spklen);
571 else
572 spk_cnt = read32(&regs->fs_spklen);
573
574 /* Find the period, rise, fall, min tlow, and min thigh in terms of
575 * counts of SoC clock. */
576 period_cnt = counts_from_freq(&soc->freq, &bus->freq);
577 rise_cnt = counts_from_time(&soc->freq, bcfg->rise_time_ns);
578 fall_cnt = counts_from_time(&soc->freq, bcfg->fall_time_ns);
579 min_tlow_cnt = counts_from_time(&soc->freq, bus->min_tlow_ns);
580 min_thigh_cnt = counts_from_time(&soc->freq, bus->min_thigh_ns);
581
582 printk(DW_I2C_DEBUG, "dw_i2c: SoC %d/%d ns Bus: %d/%d ns\n",
583 soc->freq.ticks, soc->freq.ns, bus->freq.ticks, bus->freq.ns);
584 printk(DW_I2C_DEBUG,
585 "dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
586 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
587 spk_cnt);
588
589 /*
590 * Back solve for hcnt and lcnt according to the following equations.
591 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
592 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
593 */
594 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
595 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
596
597 if (hcnt < 0 || lcnt < 0) {
598 printk(BIOS_ERR, "dw_i2c: bad counts. hcnt = %d lcnt = %d\n",
599 hcnt, lcnt);
600 return CB_ERR;
601 }
602
603 /* Now add things back up to ensure the period is hit. If off,
604 * split the difference and bias to lcnt for remainder. */
605 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
606
607 if (tot < period_cnt) {
608 diff = (period_cnt - tot) / 2;
609 hcnt += diff;
610 lcnt += diff;
611 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
612 lcnt += period_cnt - tot;
613 }
614
615 config->speed = speed;
616 config->scl_lcnt = lcnt;
617 config->scl_hcnt = hcnt;
618
619 /* Use internal default unless other value is specified. */
620 data_hold_time_ns = DEFAULT_SDA_HOLD_TIME;
621 if (bcfg->data_hold_time_ns)
622 data_hold_time_ns = bcfg->data_hold_time_ns;
623
624 config->sda_hold = counts_from_time(&soc->freq, data_hold_time_ns);
625
626 printk(DW_I2C_DEBUG, "dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n",
627 hcnt, lcnt, config->sda_hold);
628
629 return CB_SUCCESS;
630 }
631
632 enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr,
633 enum i2c_speed speed,
634 const struct dw_i2c_bus_config *bcfg,
635 struct dw_i2c_speed_config *config)
636 {
637 const int ic_clk = CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ;
638 struct dw_i2c_regs *regs;
639 int i;
640
641 regs = (struct dw_i2c_regs *)dw_i2c_addr;
642
643 _Static_assert(CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ != 0,
644 "DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ can't be zero!");
645
646 /* Apply board specific override for this speed if found */
647 for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) {
648 if (bcfg->speed_config[i].speed != speed)
649 continue;
650 memcpy(config, &bcfg->speed_config[i], sizeof(*config));
651 return CB_SUCCESS;
652 }
653
654 /* Use the time calculation. */
655 return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config);
656 }
657
658 static enum cb_err dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed,
659 const struct dw_i2c_bus_config *bcfg)
660 {
661 struct dw_i2c_regs *regs;
662 struct dw_i2c_speed_config config;
663 uint32_t control;
664
665 /* Clock must be provided by Kconfig */
666 regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
667 if (!regs || !speed)
668 return CB_ERR;
669
670 control = read32(&regs->control);
671 control &= ~CONTROL_SPEED_MASK;
672
673 if (speed >= I2C_SPEED_HIGH) {
674 /* High and Fast-Ultra speed share config registers */
675 control |= CONTROL_SPEED_HS;
676 } else if (speed >= I2C_SPEED_FAST) {
677 /* Fast speed and Fast-Plus */
678 control |= CONTROL_SPEED_FS;
679 } else {
680 /* Standard speed */
681 control |= CONTROL_SPEED_SS;
682 }
683
684 /* Generate speed config based on clock */
685 if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) != CB_SUCCESS)
686 return CB_ERR;
687
688 /* Select this speed in the control register */
689 write32(&regs->control, control);
690
691 /* Write the speed config that was generated earlier */
692 dw_i2c_set_speed_config(bus, &config);
693
694 return CB_SUCCESS;
695 }
696
697 /*
698 * Initialize this bus controller and set the speed.
699 *
700 * The bus speed can be passed in Hz or using values from device/i2c.h and
701 * will default to I2C_SPEED_FAST if it is not provided.
702 */
703 enum cb_err dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg)
704 {
705 struct dw_i2c_regs *regs;
706 enum i2c_speed speed;
707
708 if (!bcfg)
709 return CB_ERR;
710
711 speed = bcfg->speed ? : I2C_SPEED_FAST;
712
713 regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
714 if (!regs) {
715 printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
716 return CB_ERR;
717 }
718
719 if (read32(&regs->comp_type) != DW_I2C_COMP_TYPE) {
720 printk(BIOS_ERR, "I2C bus %u has unknown type 0x%x.\n", bus,
721 read32(&regs->comp_type));
722 return CB_ERR;
723 }
724
725 printk(BIOS_DEBUG, "I2C bus %u version 0x%x\n", bus, read32(&regs->comp_version));
726
727 if (dw_i2c_disable(regs) != CB_SUCCESS) {
728 printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus);
729 return CB_ERR;
730 }
731
732 /* Put controller in master mode with restart enabled */
733 write32(&regs->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE |
734 CONTROL_RESTART_ENABLE);
735
736 /* Set bus speed to FAST by default */
737 if (dw_i2c_set_speed(bus, speed, bcfg) != CB_SUCCESS) {
738 printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus);
739 return CB_ERR;
740 }
741
742 /* Set RX/TX thresholds to smallest values */
743 write32(&regs->rx_thresh, 0);
744 write32(&regs->tx_thresh, 0);
745
746 /* Enable stop detection and TX abort interrupt */
747 write32(&regs->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT);
748
749 printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n",
750 bus, regs, speed / KHz);
751
752 return CB_SUCCESS;
753 }
754
755 /*
756 * Write ACPI object to describe speed configuration.
757 *
758 * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
759 *
760 * SSCN: I2C_SPEED_STANDARD
761 * FMCN: I2C_SPEED_FAST
762 * FPCN: I2C_SPEED_FAST_PLUS
763 * HSCN: I2C_SPEED_HIGH
764 */
765 static void dw_i2c_acpi_write_speed_config(
766 const struct dw_i2c_speed_config *config)
767 {
768 if (!config)
769 return;
770 if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold)
771 return;
772
773 if (config->speed >= I2C_SPEED_HIGH)
774 acpigen_write_name("HSCN");
775 else if (config->speed >= I2C_SPEED_FAST_PLUS)
776 acpigen_write_name("FPCN");
777 else if (config->speed >= I2C_SPEED_FAST)
778 acpigen_write_name("FMCN");
779 else
780 acpigen_write_name("SSCN");
781
782 /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
783 acpigen_write_package(3);
784 acpigen_write_word(config->scl_hcnt);
785 acpigen_write_word(config->scl_lcnt);
786 acpigen_write_dword(config->sda_hold);
787 acpigen_pop_len();
788 }
789
790 /*
791 * The device should already be enabled and out of reset,
792 * either from early init in coreboot or SiliconInit in FSP.
793 */
794 void dw_i2c_dev_init(struct device *dev)
795 {
796 const struct dw_i2c_bus_config *config;
797 int bus = dw_i2c_soc_dev_to_bus(dev);
798
799 if (bus < 0)
800 return;
801
802 config = dw_i2c_get_soc_cfg(bus);
803
804 if (!config)
805 return;
806
807 dw_i2c_init(bus, config);
808 }
809
810 /*
811 * Generate I2C timing information into the SSDT for the OS driver to consume,
812 * optionally applying override values provided by the caller.
813 */
814 void dw_i2c_acpi_fill_ssdt(const struct device *dev)
815 {
816 const struct dw_i2c_bus_config *bcfg;
817 uintptr_t dw_i2c_addr;
818 struct dw_i2c_speed_config sgen;
819 int bus;
820 const char *path;
821 unsigned int speed, i;
822
823 bus = dw_i2c_soc_dev_to_bus(dev);
824
825 if (bus < 0)
826 return;
827
828 bcfg = dw_i2c_get_soc_cfg(bus);
829
830 if (!bcfg)
831 return;
832
833 dw_i2c_addr = dw_i2c_base_address(bus);
834 if (!dw_i2c_addr)
835 return;
836
837 path = acpi_device_path(dev);
838 if (!path)
839 return;
840
841 /* Ensure a default speed is available */
842 speed = (bcfg->speed == 0) ? I2C_SPEED_FAST : bcfg->speed;
843
844 /* Report currently used timing values for the OS driver */
845 acpigen_write_scope(path);
846 if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) == CB_SUCCESS) {
847 dw_i2c_acpi_write_speed_config(&sgen);
848 }
849 /* Now check if there are more speed settings available and report them as well. */
850 for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) {
851 if (bcfg->speed_config[i].speed && speed != bcfg->speed_config[i].speed)
852 dw_i2c_acpi_write_speed_config(&bcfg->speed_config[i]);
853 }
854 acpigen_write_scope_end();
855 }
856
857 static int dw_i2c_dev_transfer(struct device *dev,
858 const struct i2c_msg *msg, size_t count)
859 {
860 int bus = dw_i2c_soc_dev_to_bus(dev);
861 if (bus < 0) {
862 printk(BIOS_ERR, "Invalid I2C bus number.\n");
863 return -1;
864 }
865 return dw_i2c_transfer(bus, msg, count) == CB_SUCCESS ? 0 : -1;
866 }
867
868 const struct i2c_bus_operations dw_i2c_bus_ops = {
869 .transfer = dw_i2c_dev_transfer,
870 };
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