1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <drivers/intel/gma/i915_reg.h>
7 #include <drivers/intel/gma/gma.h>
10 /* port types. We stick with the same defines as the kernel */
11 #define INTEL_OUTPUT_UNUSED 0
12 #define INTEL_OUTPUT_ANALOG 1
13 #define INTEL_OUTPUT_DVO 2
14 #define INTEL_OUTPUT_SDVO 3
15 #define INTEL_OUTPUT_LVDS 4
16 #define INTEL_OUTPUT_TVOUT 5
17 #define INTEL_OUTPUT_HDMI 6
18 #define INTEL_OUTPUT_DISPLAYPORT 7
19 #define INTEL_OUTPUT_EDP 8
21 /* things that are, strangely, not defined anywhere? */
22 #define PCH_PP_UNLOCK 0xabcd0000
23 #define WMx_LP_SR_EN (1UL<<31)
24 #define PRB0_TAIL 0x02030
25 #define PRB0_HEAD 0x02034
26 #define PRB0_START 0x02038
27 #define PRB0_CTL 0x0203c
33 #if CONFIG(INTEL_GMA_VERSION_2)
48 #if CONFIG(INTEL_GMA_VERSION_2)
67 /* debug enums. These are for printks that, due to their place in the
68 * middle of graphics device IO, might change timing. Use with care
72 vio
= 2, /* dump every IO */
73 vspin
= 4, /* print # of times we spun on a register value */
76 /* The mainboard must provide these functions. */
77 unsigned long io_i915_read32(unsigned long addr
);
78 void io_i915_write32(unsigned long val
, unsigned long addr
);
80 void intel_prepare_ddi(void);
82 int gtt_poll(u32 reg
, u32 mask
, u32 value
);
83 void gtt_write(u32 reg
, u32 data
);
84 u32
gtt_read(u32 reg
);
89 generate_fake_intel_oprom(const struct i915_gpu_controller_info
*conf
,
90 struct device
*dev
, const char *idstr
);