src/drivers/intel/gma/intel_bios.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Authors:
   4  *    Eric Anholt <eric@anholt.net>
   5  *
   6  */
   7
   8 #ifndef _I830_BIOS_H_
   9 #define _I830_BIOS_H_
  10
  11 struct vbt_header {
  12         u8 signature[20];               /**< Always starts with 'VBT$' */
  13         u16 version;                    /**< decimal */
  14         u16 header_size;                /**< in bytes */
  15         u16 vbt_size;                   /**< in bytes */
  16         u8 vbt_checksum;
  17         u8 reserved0;
  18         u32 bdb_offset;                 /**< from beginning of VBT */
  19         u32 aim_offset[4];              /**< from beginning of VBT */
  20 } __packed;
  21
  22 struct bdb_header {
  23         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  24         u16 version;                    /**< decimal */
  25         u16 header_size;                /**< in bytes */
  26         u16 bdb_size;                   /**< in bytes */
  27 };
  28
  29 /* strictly speaking, this is a "skip" block, but it has interesting info */
  30 struct vbios_data {
  31         u8 type; /* 0 == desktop, 1 == mobile */
  32         u8 relstage;
  33         u8 chipset;
  34         u8 lvds_present:1;
  35         u8 tv_present:1;
  36         u8 rsvd2:6; /* finish byte */
  37         u8 rsvd3[4];
  38         u8 signon[155];
  39         u8 copyright[61];
  40         u16 code_segment;
  41         u8 dos_boot_mode;
  42         u8 bandwidth_percent;
  43         u8 rsvd4; /* popup memory size */
  44         u8 resize_pci_bios;
  45         u8 rsvd5; /* is crt already on ddc2 */
  46 } __packed;
  47
  48 /*
  49  * There are several types of BIOS data blocks (BDBs), each block has
  50  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  51  * Known types are listed below.
  52  */
  53 #define BDB_GENERAL_FEATURES      1
  54 #define BDB_GENERAL_DEFINITIONS   2
  55 #define BDB_OLD_TOGGLE_LIST       3
  56 #define BDB_MODE_SUPPORT_LIST     4
  57 #define BDB_GENERIC_MODE_TABLE    5
  58 #define BDB_EXT_MMIO_REGS         6
  59 #define BDB_SWF_IO                7
  60 #define BDB_SWF_MMIO              8
  61 #define BDB_DOT_CLOCK_TABLE       9
  62 #define BDB_MODE_REMOVAL_TABLE   10
  63 #define BDB_CHILD_DEVICE_TABLE   11
  64 #define BDB_DRIVER_FEATURES      12
  65 #define BDB_DRIVER_PERSISTENCE   13
  66 #define BDB_EXT_TABLE_PTRS       14
  67 #define BDB_DOT_CLOCK_OVERRIDE   15
  68 #define BDB_DISPLAY_SELECT       16
  69 /* 17 rsvd */
  70 #define BDB_DRIVER_ROTATION      18
  71 #define BDB_DISPLAY_REMOVE       19
  72 #define BDB_OEM_CUSTOM           20
  73 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  74 #define BDB_SDVO_LVDS_OPTIONS    22
  75 #define BDB_SDVO_PANEL_DTDS      23
  76 #define BDB_SDVO_LVDS_PNP_IDS    24
  77 #define BDB_SDVO_LVDS_POWER_SEQ  25
  78 #define BDB_TV_OPTIONS           26
  79 #define BDB_EDP                  27
  80 #define BDB_LVDS_OPTIONS         40
  81 #define BDB_LVDS_LFP_DATA_PTRS   41
  82 #define BDB_LVDS_LFP_DATA        42
  83 #define BDB_LVDS_BACKLIGHT       43
  84 #define BDB_LVDS_POWER           44
  85 #define BDB_MIPI                 50
  86 #define BDB_SKIP                254 /* VBIOS private block, ignore */
  87
  88 struct bdb_general_features {
  89         /* bits 1 */
  90         u8 panel_fitting:2;
  91         u8 flexaim:1;
  92         u8 msg_enable:1;
  93         u8 clear_screen:3;
  94         u8 color_flip:1;
  95
  96         /* bits 2 */
  97         u8 download_ext_vbt:1;
  98         u8 enable_ssc:1;
  99         u8 ssc_freq:1;
 100         u8 enable_lfp_on_override:1;
 101         u8 disable_ssc_ddt:1;
 102         u8 rsvd7:1;
 103         u8 display_clock_mode:1;
 104         u8 rsvd8:1; /* finish byte */
 105
 106         /* bits 3 */
 107         u8 disable_smooth_vision:1;
 108         u8 single_dvi:1;
 109         u8 rsvd9:1;
 110         u8 fdi_rx_polarity_inverted:1;
 111         u8 rsvd10:4; /* finish byte */
 112
 113         /* bits 4 */
 114         u8 legacy_monitor_detect;
 115
 116         /* bits 5 */
 117         u8 int_crt_support:1;
 118         u8 int_tv_support:1;
 119         u8 int_efp_support:1;
 120         u8 dp_ssc_enb:1;        /* PCH attached eDP supports SSC */
 121         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 122         u8 rsvd11:3; /* finish byte */
 123 } __packed;
 124
 125 /* pre-915 */
 126 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 127 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 128 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 129 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 130
 131 /* Pre 915 */
 132 #define DEVICE_TYPE_NONE        0x00
 133 #define DEVICE_TYPE_CRT         0x01
 134 #define DEVICE_TYPE_TV          0x09
 135 #define DEVICE_TYPE_EFP         0x12
 136 #define DEVICE_TYPE_LFP         0x22
 137 /* On 915+ */
 138 #define DEVICE_TYPE_CRT_DPMS            0x6001
 139 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 140 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 141 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 142 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 143 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 144 #define DEVICE_TYPE_TV_SCART            0x0209
 145 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 146 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 147 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 148 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 149 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 150 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 151 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 152 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 153 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 154 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 155 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 156 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 157 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 158
 159 #define DEVICE_CFG_NONE         0x00
 160 #define DEVICE_CFG_12BIT_DVOB   0x01
 161 #define DEVICE_CFG_12BIT_DVOC   0x02
 162 #define DEVICE_CFG_24BIT_DVOBC  0x09
 163 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 164 #define DEVICE_CFG_DUAL_DVOB    0x11
 165 #define DEVICE_CFG_DUAL_DVOC    0x12
 166 #define DEVICE_CFG_DUAL_DVOBC   0x13
 167 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 168 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 169
 170 #define DEVICE_WIRE_NONE        0x00
 171 #define DEVICE_WIRE_DVOB        0x01
 172 #define DEVICE_WIRE_DVOC        0x02
 173 #define DEVICE_WIRE_DVOBC       0x03
 174 #define DEVICE_WIRE_DVOBB       0x05
 175 #define DEVICE_WIRE_DVOCC       0x06
 176 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 177 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 178
 179 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 180 #define DEVICE_PORT_DVOB        0x01
 181 #define DEVICE_PORT_DVOC        0x02
 182
 183 /* We used to keep this struct but without any version control. We should avoid
 184  * using it in the future, but it should be safe to keep using it in the old
 185  * code. */
 186 struct old_child_dev_config {
 187         u16 handle;
 188         u16 device_type;
 189         u8  device_id[10]; /* ascii string */
 190         u16 addin_offset;
 191         u8  dvo_port; /* See Device_PORT_* above */
 192         u8  i2c_pin;
 193         u8  slave_addr;
 194         u8  ddc_pin;
 195         u16 edid_ptr;
 196         u8  dvo_cfg; /* See DEVICE_CFG_* above */
 197         u8  dvo2_port;
 198         u8  i2c2_pin;
 199         u8  slave2_addr;
 200         u8  ddc2_pin;
 201         u8  capabilities;
 202         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
 203         u8  dvo2_wiring;
 204         u16 extended_type;
 205         u8  dvo_function;
 206 } __packed;
 207
 208 /* This one contains field offsets that are known to be common for all BDB
 209  * versions. Notice that the meaning of the contents may still change, but
 210  * at least the offsets are consistent. */
 211 struct common_child_dev_config {
 212         u16 handle;
 213         u16 device_type;
 214         u8 not_common1[12];
 215         u8 dvo_port;
 216         u8 not_common2[2];
 217         u8 ddc_pin;
 218         u16 edid_ptr;
 219 } __packed;
 220
 221 /* This field changes depending on the BDB version, so the most reliable way to
 222  * read it is by checking the BDB version and reading the raw pointer. */
 223 union child_device_config {
 224         /* This one is safe to be used anywhere, but the code should still check
 225          * the BDB version. */
 226         u8 raw[33];
 227         /* This one should only be kept for legacy code. */
 228         struct old_child_dev_config old;
 229         /* This one should also be safe to use anywhere, even without version
 230          * checks. */
 231         struct common_child_dev_config common;
 232 };
 233
 234 struct bdb_general_definitions {
 235         /* DDC GPIO */
 236         u8 crt_ddc_gmbus_pin;
 237
 238         /* DPMS bits */
 239         u8 dpms_acpi:1;
 240         u8 skip_boot_crt_detect:1;
 241         u8 dpms_aim:1;
 242         u8 rsvd1:5; /* finish byte */
 243
 244         /* boot device bits */
 245         u8 boot_display[2];
 246         u8 child_dev_size;
 247
 248         /*
 249          * Device info:
 250          * If TV is present, it'll be at devices[0].
 251          * LVDS will be next, either devices[0] or [1], if present.
 252          * On some platforms the number of device is 6. But could be as few as
 253          * 4 if both TV and LVDS are missing.
 254          * And the device num is related with the size of general definition
 255          * block. It is obtained by using the following formula:
 256          * number = (block_size - sizeof(bdb_general_definitions))/
 257          *           sizeof(child_device_config);
 258          */
 259         union child_device_config devices[];
 260 } __packed;
 261
 262 struct bdb_lvds_options {
 263         u8 panel_type;
 264         u8 rsvd1;
 265         /* LVDS capabilities, stored in a dword */
 266         u8 pfit_mode:2;
 267         u8 pfit_text_mode_enhanced:1;
 268         u8 pfit_gfx_mode_enhanced:1;
 269         u8 pfit_ratio_auto:1;
 270         u8 pixel_dither:1;
 271         u8 lvds_edid:1;
 272         u8 rsvd2:1;
 273         u8 rsvd4;
 274 } __packed;
 275
 276 /* LFP pointer table contains entries to the struct below */
 277 struct bdb_lvds_lfp_data_ptr {
 278         u16 fp_timing_offset; /* offsets are from start of bdb */
 279         u8 fp_table_size;
 280         u16 dvo_timing_offset;
 281         u8 dvo_table_size;
 282         u16 panel_pnp_id_offset;
 283         u8 pnp_table_size;
 284 } __packed;
 285
 286 struct bdb_lvds_lfp_data_ptrs {
 287         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 288         struct bdb_lvds_lfp_data_ptr ptr[16];
 289 } __packed;
 290
 291 /* LFP data has 3 blocks per entry */
 292 struct lvds_fp_timing {
 293         u16 x_res;
 294         u16 y_res;
 295         u32 lvds_reg;
 296         u32 lvds_reg_val;
 297         u32 pp_on_reg;
 298         u32 pp_on_reg_val;
 299         u32 pp_off_reg;
 300         u32 pp_off_reg_val;
 301         u32 pp_cycle_reg;
 302         u32 pp_cycle_reg_val;
 303         u32 pfit_reg;
 304         u32 pfit_reg_val;
 305         u16 terminator;
 306 } __packed;
 307
 308 struct lvds_dvo_timing {
 309         u16 clock;              /**< In 10khz */
 310         u8 hactive_lo;
 311         u8 hblank_lo;
 312         u8 hblank_hi:4;
 313         u8 hactive_hi:4;
 314         u8 vactive_lo;
 315         u8 vblank_lo;
 316         u8 vblank_hi:4;
 317         u8 vactive_hi:4;
 318         u8 hsync_off_lo;
 319         u8 hsync_pulse_width;
 320         u8 vsync_pulse_width:4;
 321         u8 vsync_off:4;
 322         u8 rsvd0:6;
 323         u8 hsync_off_hi:2;
 324         u8 h_image;
 325         u8 v_image;
 326         u8 max_hv;
 327         u8 h_border;
 328         u8 v_border;
 329         u8 rsvd1:3;
 330         u8 digital:2;
 331         u8 vsync_positive:1;
 332         u8 hsync_positive:1;
 333         u8 rsvd2:1;
 334 } __packed;
 335
 336 struct lvds_pnp_id {
 337         u16 mfg_name;
 338         u16 product_code;
 339         u32 serial;
 340         u8 mfg_week;
 341         u8 mfg_year;
 342 } __packed;
 343
 344 struct bdb_lvds_lfp_data_entry {
 345         struct lvds_fp_timing fp_timing;
 346         struct lvds_dvo_timing dvo_timing;
 347         struct lvds_pnp_id pnp_id;
 348 } __packed;
 349
 350 struct bdb_lvds_lfp_data {
 351         struct bdb_lvds_lfp_data_entry data[16];
 352 } __packed;
 353
 354 struct aimdb_header {
 355         char signature[16];
 356         char oem_device[20];
 357         u16 aimdb_version;
 358         u16 aimdb_header_size;
 359         u16 aimdb_size;
 360 } __packed;
 361
 362 struct aimdb_block {
 363         u8 aimdb_id;
 364         u16 aimdb_size;
 365 } __packed;
 366
 367 struct vch_panel_data {
 368         u16 fp_timing_offset;
 369         u8 fp_timing_size;
 370         u16 dvo_timing_offset;
 371         u8 dvo_timing_size;
 372         u16 text_fitting_offset;
 373         u8 text_fitting_size;
 374         u16 graphics_fitting_offset;
 375         u8 graphics_fitting_size;
 376 } __packed;
 377
 378 struct vch_bdb_22 {
 379         struct aimdb_block aimdb_block;
 380         struct vch_panel_data panels[16];
 381 } __packed;
 382
 383 struct bdb_sdvo_lvds_options {
 384         u8 panel_backlight;
 385         u8 h40_set_panel_type;
 386         u8 panel_type;
 387         u8 ssc_clk_freq;
 388         u16 als_low_trip;
 389         u16 als_high_trip;
 390         u8 sclalarcoeff_tab_row_num;
 391         u8 sclalarcoeff_tab_row_size;
 392         u8 coefficient[8];
 393         u8 panel_misc_bits_1;
 394         u8 panel_misc_bits_2;
 395         u8 panel_misc_bits_3;
 396         u8 panel_misc_bits_4;
 397 } __packed;
 398
 399 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 400 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 401 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 402 #define BDB_DRIVER_FEATURE_EDP                  3
 403
 404 struct bdb_driver_features {
 405         u8 boot_dev_algorithm:1;
 406         u8 block_display_switch:1;
 407         u8 allow_display_switch:1;
 408         u8 hotplug_dvo:1;
 409         u8 dual_view_zoom:1;
 410         u8 int15h_hook:1;
 411         u8 sprite_in_clone:1;
 412         u8 primary_lfp_id:1;
 413
 414         u16 boot_mode_x;
 415         u16 boot_mode_y;
 416         u8 boot_mode_bpp;
 417         u8 boot_mode_refresh;
 418
 419         u16 enable_lfp_primary:1;
 420         u16 selective_mode_pruning:1;
 421         u16 dual_frequency:1;
 422         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 423         u16 nt_clone_support:1;
 424         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 425         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 426         u16 cui_aspect_scaling:1;
 427         u16 preserve_aspect_ratio:1;
 428         u16 sdvo_device_power_down:1;
 429         u16 crt_hotplug:1;
 430         u16 lvds_config:2;
 431         u16 tv_hotplug:1;
 432         u16 hdmi_config:2;
 433
 434         u8 static_display:1;
 435         u8 reserved2:7;
 436         u16 legacy_crt_max_x;
 437         u16 legacy_crt_max_y;
 438         u8 legacy_crt_max_refresh;
 439
 440         u8 hdmi_termination;
 441         u8 custom_vbt_version;
 442 } __packed;
 443
 444 #define EDP_18BPP       0
 445 #define EDP_24BPP       1
 446 #define EDP_30BPP       2
 447 #define EDP_RATE_1_62   0
 448 #define EDP_RATE_2_7    1
 449 #define EDP_LANE_1      0
 450 #define EDP_LANE_2      1
 451 #define EDP_LANE_4      3
 452 #define EDP_PREEMPHASIS_NONE    0
 453 #define EDP_PREEMPHASIS_3_5dB   1
 454 #define EDP_PREEMPHASIS_6dB     2
 455 #define EDP_PREEMPHASIS_9_5dB   3
 456 #define EDP_VSWING_0_4V         0
 457 #define EDP_VSWING_0_6V         1
 458 #define EDP_VSWING_0_8V         2
 459 #define EDP_VSWING_1_2V         3
 460
 461 struct edp_power_seq {
 462         u16 t1_t3;
 463         u16 t8;
 464         u16 t9;
 465         u16 t10;
 466         u16 t11_t12;
 467 } __packed;
 468
 469 struct edp_link_params {
 470         u8 rate:4;
 471         u8 lanes:4;
 472         u8 preemphasis:4;
 473         u8 vswing:4;
 474 } __packed;
 475
 476 struct bdb_edp {
 477         struct edp_power_seq power_seqs[16];
 478         u32 color_depth;
 479         struct edp_link_params link_params[16];
 480         u32 sdrrs_msa_timing_delay;
 481
 482         /* ith bit indicates enabled/disabled for (i+1)th panel */
 483         u16 edp_s3d_feature;
 484         u16 edp_t3_optimization;
 485 } __packed;
 486
 487 /*
 488  * Driver<->VBIOS interaction occurs through scratch bits in
 489  * GR18 & SWF*.
 490  */
 491
 492 /* GR18 bits are set on display switch and hotkey events */
 493 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 494 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 495 #define   GR18_HK_NONE          (0x0<<3)
 496 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 497 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 498 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 499 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 500 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 501 #define   GR18_HK_PFIT          (0x8<<3)
 502 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 503 #define   GR18_HK_MULTIPLE      (0xc<<3)
 504 #define GR18_USER_INT_EN        (1<<2)
 505 #define GR18_A0000_FLUSH_EN     (1<<1)
 506 #define GR18_SMM_EN             (1<<0)
 507
 508 /* Set by driver, cleared by VBIOS */
 509 #define SWF00_YRES_SHIFT        16
 510 #define SWF00_XRES_SHIFT        0
 511 #define SWF00_RES_MASK          0xffff
 512
 513 /* Set by VBIOS at boot time and driver at runtime */
 514 #define SWF01_TV2_FORMAT_SHIFT  8
 515 #define SWF01_TV1_FORMAT_SHIFT  0
 516 #define SWF01_TV_FORMAT_MASK    0xffff
 517
 518 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 519 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 520 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 521 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 522 #define   SWF10_OLD_TOGGLE      0x0
 523 #define   SWF10_TOGGLE_LIST_1   0x1
 524 #define   SWF10_TOGGLE_LIST_2   0x2
 525 #define   SWF10_TOGGLE_LIST_3   0x3
 526 #define   SWF10_TOGGLE_LIST_4   0x4
 527 #define SWF10_PANNING_EN        (1<<23)
 528 #define SWF10_DRIVER_LOADED     (1<<22)
 529 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 530 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 531 #define SWF10_OVERLAY_EN        (1<<19)
 532 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 533 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 534 #define SWF10_VGA_HOLDOFF       (1<<16)
 535 #define SWF10_ACTIVE_DISP_MASK  0xffff
 536 #define   SWF10_PIPEB_LFP2      (1<<15)
 537 #define   SWF10_PIPEB_EFP2      (1<<14)
 538 #define   SWF10_PIPEB_TV2       (1<<13)
 539 #define   SWF10_PIPEB_CRT2      (1<<12)
 540 #define   SWF10_PIPEB_LFP       (1<<11)
 541 #define   SWF10_PIPEB_EFP       (1<<10)
 542 #define   SWF10_PIPEB_TV        (1<<9)
 543 #define   SWF10_PIPEB_CRT       (1<<8)
 544 #define   SWF10_PIPEA_LFP2      (1<<7)
 545 #define   SWF10_PIPEA_EFP2      (1<<6)
 546 #define   SWF10_PIPEA_TV2       (1<<5)
 547 #define   SWF10_PIPEA_CRT2      (1<<4)
 548 #define   SWF10_PIPEA_LFP       (1<<3)
 549 #define   SWF10_PIPEA_EFP       (1<<2)
 550 #define   SWF10_PIPEA_TV        (1<<1)
 551 #define   SWF10_PIPEA_CRT       (1<<0)
 552
 553 #define SWF11_MEMORY_SIZE_SHIFT 16
 554 #define SWF11_SV_TEST_EN        (1<<15)
 555 #define SWF11_IS_AGP            (1<<14)
 556 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 557 #define SWF11_DPMS_REDUCED      (1<<12)
 558 #define SWF11_IS_VBE_MODE       (1<<11)
 559 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 560 #define SWF11_DPMS_MASK         0x07
 561 #define   SWF11_DPMS_OFF        (1<<2)
 562 #define   SWF11_DPMS_SUSPEND    (1<<1)
 563 #define   SWF11_DPMS_STANDBY    (1<<0)
 564 #define   SWF11_DPMS_ON         0
 565
 566 #define SWF14_GFX_PFIT_EN       (1UL<<31)
 567 #define SWF14_TEXT_PFIT_EN      (1<<30)
 568 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 569 #define SWF14_POPUP_EN          (1<<28)
 570 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 571 #define SWF14_DISP_DETECT_EN    (1<<26)
 572 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 573 #define SWF14_DRIVER_STATUS     (1<<24)
 574 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 575 #define SWF14_OS_TYPE_WINNT     (1<<22)
 576 /* 21:19 rsvd */
 577 #define SWF14_PM_TYPE_MASK      0x00070000
 578 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 579 #define   SWF14_PM_ACPI         (0x3 << 16)
 580 #define   SWF14_PM_APM_12       (0x2 << 16)
 581 #define   SWF14_PM_APM_11       (0x1 << 16)
 582 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 583           /* if GR18 indicates a display switch */
 584 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 585 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 586 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 587 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 588 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 589 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 590 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 591 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 592 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 593 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 594 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 595 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 596 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 597 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 598 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 599 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 600           /* if GR18 indicates a panel fitting request */
 601 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 602           /* if GR18 indicates an APM change request */
 603 #define   SWF14_APM_HIBERNATE   0x4
 604 #define   SWF14_APM_SUSPEND     0x3
 605 #define   SWF14_APM_STANDBY     0x1
 606 #define   SWF14_APM_RESTORE     0x0
 607
 608 /* Add the device class for LFP, TV, HDMI */
 609 #define  DEVICE_TYPE_INT_LFP    0x1022
 610 #define  DEVICE_TYPE_INT_TV     0x1009
 611 #define  DEVICE_TYPE_HDMI       0x60D2
 612 #define  DEVICE_TYPE_DP         0x68C6
 613 #define  DEVICE_TYPE_eDP        0x78C6
 614
 615 #define  DEVICE_TYPE_CLASS_EXTENSION    (1 << 15)
 616 #define  DEVICE_TYPE_POWER_MANAGEMENT   (1 << 14)
 617 #define  DEVICE_TYPE_HOTPLUG_SIGNALING  (1 << 13)
 618 #define  DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
 619 #define  DEVICE_TYPE_NOT_HDMI_OUTPUT    (1 << 11)
 620 #define  DEVICE_TYPE_MIPI_OUTPUT        (1 << 10)
 621 #define  DEVICE_TYPE_COMPOSITE_OUTPUT   (1 << 9)
 622 #define  DEVICE_TYPE_DUAL_CHANNEL       (1 << 8)
 623 #define  DEVICE_TYPE_HIGH_SPEED_LINK    (1 << 6)
 624 #define  DEVICE_TYPE_LVDS_SINGALING     (1 << 5)
 625 #define  DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
 626 #define  DEVICE_TYPE_VIDEO_SIGNALING    (1 << 3)
 627 #define  DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
 628 #define  DEVICE_TYPE_DIGITAL_OUTPUT     (1 << 1)
 629 #define  DEVICE_TYPE_ANALOG_OUTPUT      (1 << 0)
 630
 631 /*
 632  * Bits we care about when checking for DEVICE_TYPE_eDP
 633  * Depending on the system, the other bits may or may not
 634  * be set for eDP outputs.
 635  */
 636 #define DEVICE_TYPE_eDP_BITS \
 637         (DEVICE_TYPE_INTERNAL_CONNECTOR | \
 638          DEVICE_TYPE_NOT_HDMI_OUTPUT | \
 639          DEVICE_TYPE_MIPI_OUTPUT | \
 640          DEVICE_TYPE_COMPOSITE_OUTPUT | \
 641          DEVICE_TYPE_DUAL_CHANNEL | \
 642          DEVICE_TYPE_LVDS_SINGALING | \
 643          DEVICE_TYPE_TMDS_DVI_SIGNALING | \
 644          DEVICE_TYPE_VIDEO_SIGNALING | \
 645          DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
 646          DEVICE_TYPE_DIGITAL_OUTPUT | \
 647          DEVICE_TYPE_ANALOG_OUTPUT)
 648
 649 /* define the DVO port for HDMI output type */
 650 #define         DVO_B           1
 651 #define         DVO_C           2
 652 #define         DVO_D           3
 653
 654 /* define the PORT for DP output type */
 655 #define         PORT_IDPB       7
 656 #define         PORT_IDPC       8
 657 #define         PORT_IDPD       9
 658
 659 /* Possible values for the "DVO Port" field for versions >= 155: */
 660 #define DVO_PORT_HDMIA  0
 661 #define DVO_PORT_HDMIB  1
 662 #define DVO_PORT_HDMIC  2
 663 #define DVO_PORT_HDMID  3
 664 #define DVO_PORT_LVDS   4
 665 #define DVO_PORT_TV     5
 666 #define DVO_PORT_CRT    6
 667 #define DVO_PORT_DPB    7
 668 #define DVO_PORT_DPC    8
 669 #define DVO_PORT_DPD    9
 670 #define DVO_PORT_DPA    10
 671
 672 /* MIPI DSI panel info */
 673 struct bdb_mipi {
 674         u16 panel_id;
 675         u16 bridge_revision;
 676
 677         /* General params */
 678         u32 dithering:1;
 679         u32 bpp_pixel_format:1;
 680         u32 rsvd1:1;
 681         u32 dphy_valid:1;
 682         u32 resvd2:28;
 683
 684         u16 port_info;
 685         u16 rsvd3:2;
 686         u16 num_lanes:2;
 687         u16 rsvd4:12;
 688
 689         /* DSI config */
 690         u16 virt_ch_num:2;
 691         u16 vtm:2;
 692         u16 rsvd5:12;
 693
 694         u32 dsi_clock;
 695         u32 bridge_ref_clk;
 696         u16 rsvd_pwr;
 697
 698         /* Dphy Params */
 699         u32 prepare_cnt:5;
 700         u32 rsvd6:3;
 701         u32 clk_zero_cnt:8;
 702         u32 trail_cnt:5;
 703         u32 rsvd7:3;
 704         u32 exit_zero_cnt:6;
 705         u32 rsvd8:2;
 706
 707         u32 hl_switch_cnt;
 708         u32 lp_byte_clk;
 709         u32 clk_lane_switch_cnt;
 710 } __packed;
 711
 712 #define VBT_SIGNATURE 0x54425624
 713
 714 #endif /* _I830_BIOS_H_ */