src/drivers/uart/uart8250mem.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <console/uart.h>
   6 #include <device/device.h>
   7 #include <delay.h>
   8 #include <stdint.h>
   9 #include "uart8250reg.h"
  10
  11 /* Should support 8250, 16450, 16550, 16550A type UARTs */
  12
  13 /* Expected character delay at 1200bps is 9ms for a working UART
  14  * and no flow-control. Assume UART as stuck if shift register
  15  * or FIFO takes more than 50ms per character to appear empty.
  16  */
  17 #define SINGLE_CHAR_TIMEOUT     (50 * 1000)
  18 #define FIFO_TIMEOUT            (16 * SINGLE_CHAR_TIMEOUT)
  19
  20 #if CONFIG(DRIVERS_UART_8250MEM_32)
  21 static uint8_t uart8250_read(void *base, uint8_t reg)
  22 {
  23         return read32(base + 4 * reg) & 0xff;
  24 }
  25
  26 static void uart8250_write(void *base, uint8_t reg, uint8_t data)
  27 {
  28         write32(base + 4 * reg, data);
  29 }
  30 #else
  31 static uint8_t uart8250_read(void *base, uint8_t reg)
  32 {
  33         return read8(base + reg);
  34 }
  35
  36 static void uart8250_write(void *base, uint8_t reg, uint8_t data)
  37 {
  38         write8(base + reg, data);
  39 }
  40 #endif
  41
  42 static int uart8250_mem_can_tx_byte(void *base)
  43 {
  44         return uart8250_read(base, UART8250_LSR) & UART8250_LSR_THRE;
  45 }
  46
  47 static void uart8250_mem_tx_byte(void *base, unsigned char data)
  48 {
  49         unsigned long int i = SINGLE_CHAR_TIMEOUT;
  50         while (i-- && !uart8250_mem_can_tx_byte(base))
  51                 udelay(1);
  52         uart8250_write(base, UART8250_TBR, data);
  53 }
  54
  55 static void uart8250_mem_tx_flush(void *base)
  56 {
  57         unsigned long int i = FIFO_TIMEOUT;
  58         while (i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT))
  59                 udelay(1);
  60 }
  61
  62 static int uart8250_mem_can_rx_byte(void *base)
  63 {
  64         return uart8250_read(base, UART8250_LSR) & UART8250_LSR_DR;
  65 }
  66
  67 static unsigned char uart8250_mem_rx_byte(void *base)
  68 {
  69         unsigned long int i = SINGLE_CHAR_TIMEOUT;
  70         while (i && !uart8250_mem_can_rx_byte(base)) {
  71                 udelay(1);
  72                 i--;
  73         }
  74         if (i)
  75                 return uart8250_read(base, UART8250_RBR);
  76         else
  77                 return 0x0;
  78 }
  79
  80 static void uart8250_mem_init(void *base, unsigned int divisor)
  81 {
  82         /* Disable interrupts */
  83         uart8250_write(base, UART8250_IER, 0x0);
  84         /* Enable FIFOs */
  85         uart8250_write(base, UART8250_FCR, UART8250_FCR_FIFO_EN);
  86
  87         /* Assert DTR and RTS so the other end is happy */
  88         uart8250_write(base, UART8250_MCR, UART8250_MCR_DTR | UART8250_MCR_RTS);
  89
  90         /* DLAB on */
  91         uart8250_write(base, UART8250_LCR, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
  92
  93         uart8250_write(base, UART8250_DLL, divisor & 0xFF);
  94         uart8250_write(base, UART8250_DLM, (divisor >> 8) & 0xFF);
  95
  96         /* Set to 3 for 8N1 */
  97         uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS);
  98 }
  99
 100 void uart_init(unsigned int idx)
 101 {
 102         void *base = uart_platform_baseptr(idx);
 103         if (!base)
 104                 return;
 105
 106         unsigned int div;
 107         div = uart_baudrate_divisor(get_uart_baudrate(),
 108                 uart_platform_refclk(), uart_input_clock_divider());
 109         uart8250_mem_init(base, div);
 110 }
 111
 112 void uart_tx_byte(unsigned int idx, unsigned char data)
 113 {
 114         void *base = uart_platform_baseptr(idx);
 115         if (!base)
 116                 return;
 117         uart8250_mem_tx_byte(base, data);
 118 }
 119
 120 unsigned char uart_rx_byte(unsigned int idx)
 121 {
 122         void *base = uart_platform_baseptr(idx);
 123         if (!base)
 124                 return 0xff;
 125         return uart8250_mem_rx_byte(base);
 126 }
 127
 128 void uart_tx_flush(unsigned int idx)
 129 {
 130         void *base = uart_platform_baseptr(idx);
 131         if (!base)
 132                 return;
 133         uart8250_mem_tx_flush(base);
 134 }
 135
 136 enum cb_err fill_lb_serial(struct lb_serial *serial)
 137 {
 138         serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 139         serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 140         if (!serial->baseaddr)
 141                 return CB_ERR;
 142         serial->baud = get_uart_baudrate();
 143         if (CONFIG(DRIVERS_UART_8250MEM_32))
 144                 serial->regwidth = sizeof(uint32_t);
 145         else
 146                 serial->regwidth = sizeof(uint8_t);
 147         serial->input_hertz = uart_platform_refclk();
 148
 149         return CB_SUCCESS;
 150 }