mb/google/brya: Create rull variant

[coreboot2.git] / src / mainboard / asus / p2b / variants / p3b-f / overridetree.cb

chip northbridge/intel/i440bx           # Northbridge
        device domain 0 on              # PCI domain
                chip southbridge/intel/i82371eb # Southbridge
                        register "gpo" = "0x67ffbfff"   # GPIO: This value sets GPIOs 27,28 to expose HWM
                        device pci 4.0 on                       # ISA bridge
                                chip superio/winbond/w83977tf   # Super I/O
                                device pnp 3f0.a off end        # ACPI
                                end
                        end
                end
        end
end