1 ## SPDX
-License
-Identifier
: GPL
-2.0-only
3 chip northbridge
/intel
/sandybridge
4 # All MRC
-capable boards in family
(P8Z77
-M
[ PRO
]) lists supported
6 register
"ddr3lv_support" = "1"
7 register
"max_mem_clock_mhz" = "800"
8 register
"spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
10 #
4 bit switch mask.
0=not switchable
, 1=switchable
11 # Means once it
's loaded the OS, it can swap ports
12 # from
/to EHCI
/xHCI. Z77 has four USB3 ports
, so
0xf
13 register
"usb3.hs_port_switch_mask" = "0xf"
14 #
(The other
3 usb3.
* settings can be
set from nvram options
, and so are
set
18 device ref host_bridge on
end
19 device ref peg10 on
end # PCIEX16_1
22 chip southbridge
/intel
/bd82x6x
23 register
"sata_interface_speed_support" = "0x3"
24 register
"sata_port_map" = "0x3f"
25 register
"spi_lvscc" = "0x2005"
26 register
"spi_uvscc" = "0x2005"
27 register
"superspeed_capable_ports" = "0x0000000f"
28 register
"xhci_overcurrent_mapping" = "0x00000c03"
29 register
"xhci_switchable_ports" = "0x0000000f"
31 device ref xhci on
end
32 device ref mei1 on
end
33 device ref mei2 off
end
34 device ref me_ide_r off
end
35 device ref me_kt off
end
36 device ref gbe off
end
37 device ref ehci2 on
end
40 device ref pcie_rp1 off
end
41 device ref pcie_rp2 off
end
42 device ref pcie_rp3 off
end
43 device ref pcie_rp4 off
end
44 device ref pcie_rp5 off
end
45 device ref pcie_rp6 off
end
46 device ref pcie_rp7 off
end
47 device ref pcie_rp8 off
end
49 device ref ehci1 on
end
50 device ref pci_bridge off
end
52 device ref sata1 on
end # SATA
(AHCI
)
53 device ref smbus on
end
54 device ref sata2 off
end # SATA
(Legacy
)
55 device ref thermal off
end