src/mainboard/erying/tgl/devicetree.cb

   1 chip soc/intel/tigerlake
   2
   3         # Power limits/thermals - adjust according to your needs, but beware of VRM cooling!
   4         # H_6_CORE means Core i5, H_8_CORE means Core i7 or i9. Stock PL1/PL2: 45/109W.
   5         register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
   6                 .tdp_pl1_override = 45,
   7                 .tdp_pl2_override = 109,
   8         }"
   9
  10         register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
  11                 .tdp_pl1_override = 45,
  12                 .tdp_pl2_override = 109,
  13         }"
  14         register "tcc_offset" = "8"
  15
  16         # FSP configuration
  17         register "eist_enable" = "1"
  18         register "enable_c6dram" = "1"
  19
  20         register "deep_s3_enable_ac" = "1"
  21         register "deep_s3_enable_dc" = "1"
  22         register "deep_s5_enable_ac" = "1"
  23         register "deep_s5_enable_dc" = "1"
  24
  25         # PME routing
  26         register "pmc_gpe0_dw0" = "PMC_GPP_R"
  27         register "pmc_gpe0_dw1" = "PMC_GPP_B"
  28         register "pmc_gpe0_dw2" = "PMC_GPP_D"
  29
  30         # FiVR External Rails
  31         register "ext_fivr_settings" = "{
  32                 .configure_ext_fivr = 1,
  33                 .v1p05_enable_bitmap = 0,
  34                 .vnn_enable_bitmap = 0,
  35                 .v1p05_supported_voltage_bitmap = 0,
  36                 .vnn_supported_voltage_bitmap = 0,
  37                 .v1p05_icc_max_ma = 500,
  38                 .vnn_sx_voltage_mv = 1050,
  39         }"
  40
  41         device cpu_cluster 0 on end
  42         device domain 0 on
  43                 device ref igpu on
  44                         register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" # DP
  45                         register "DdiPortBHpd" = "1"
  46                         register "DdiPortBDdc" = "1"
  47
  48                         register "DdiPortCHpd" = "1" # HDMI
  49                         register "DdiPortCDdc" = "1"
  50
  51                         register "DdiPort1Hpd" = "1" # HDMI
  52                         register "DdiPort1Ddc" = "1"
  53                 end
  54
  55                 device ref peg0 on      # SoC M.2 (Gen4)
  56                         register "PcieClkSrcUsage[2]" = "0x40"
  57                         register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
  58                 end
  59
  60                 device ref peg1 on      # SoC x16 (Gen4)
  61                         register "PcieClkSrcUsage[0]" = "0x41"
  62                         register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
  63                 end
  64
  65                 device ref north_xhci on
  66                          register "TcssXhciEn" = "1"
  67                 end
  68
  69                 device ref south_xhci on
  70                         register "usb2_ports" = "{
  71                                 [0] = USB2_PORT_MID(OC_SKIP),           /* Rear, bottom right */
  72                                 [1] = USB2_PORT_MID(OC_SKIP),           /* Rear, bottom left */
  73                                 [2] = USB2_PORT_MID(OC_SKIP),           /* NIC left */
  74                                 [3] = USB2_PORT_MID(OC_SKIP),           /* NIC right */
  75                                 [4] = USB2_PORT_MID(OC_SKIP),           /* Front Panel 1 */
  76                                 [5] = USB2_PORT_MID(OC_SKIP),           /* Front Panel 2 */
  77                                 [8] = USB2_PORT_MID(OC_SKIP),           /* Front Panel 1 (USB3) */
  78                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Front Panel 2 (USB3) */
  79                                 [10] = USB2_PORT_MID(OC_SKIP),          /* Rear, top left */
  80                                 [11] = USB2_PORT_MID(OC_SKIP),          /* Rear, top right */
  81                         }"
  82
  83                         register "usb3_ports" = "{
  84                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* Rear, bottom right */
  85                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* Rear, bottom left */
  86                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Front Panel 1 */
  87                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* Front Panel 2 */
  88                                 [4] = USB3_PORT_DEFAULT(OC_SKIP),       /* Rear, top left */
  89                                 [5] = USB3_PORT_DEFAULT(OC_SKIP),       /* Rear, top right */
  90                         }"
  91                 end
  92
  93                 device ref shared_ram on end
  94
  95                 device ref sata on
  96                         register "SataPortsEnable" = "{
  97                                 [0] = 1,
  98                                 [1] = 1,
  99                                 [2] = 1,
 100                                 [3] = 1,
 101                         }"
 102                         register "SataPortsDevSlp" = "{
 103                                 [0] = 1,
 104                                 [1] = 1,
 105                                 [2] = 1,
 106                                 [3] = 1,
 107                         }"
 108                         register "SataSalpSupport" = "1"
 109                 end
 110
 111                 device ref pcie_rp5 on          # PCH M.2 (Gen3)
 112                         register "PcieRpSlotImplemented[4]" = "1"
 113                         register "PcieClkSrcUsage[4]" = "4"
 114                         register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
 115                 end
 116
 117                 device ref pcie_rp9 on          # PCH NGFF (WiFi)
 118                         register "PcieRpSlotImplemented[8]" = "1"
 119                         register "PcieClkSrcUsage[5]" = "8"
 120                         register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 121
 122                 end
 123
 124                 device ref pcie_rp11 on         # RTL8111 GbE
 125                         register "PcieClkSrcUsage[3]" = "10"
 126                         register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
 127                 end
 128
 129                 device ref pcie_rp12 on         # PCH x1 (Gen3)
 130                         register "PcieRpSlotImplemented[11]" = "1"
 131                         register "PcieClkSrcUsage[1]" = "11"
 132                         register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
 133                 end
 134
 135                 device ref pch_espi on
 136                         chip superio/ite/it8613e
 137                                 device pnp 2e.0 off end
 138                                 device pnp 2e.1 on      # COM 1
 139                                         io 0x60 = 0x3f8
 140                                         irq 0x70 = 4
 141                                         irq 0xf0 = 1
 142                                 end
 143
 144                                 device pnp 2e.4 on      # Environment Controller
 145                                         io 0x60 = 0xa30
 146                                         io 0x62 = 0xa20
 147                                         irq 0x70 = 0x00
 148                                         irq 0xf4 = 0xe0
 149                                         irq 0xf5 = 0x00
 150                                         irq 0xf6 = 0xf0
 151
 152                                         register "TMPIN1.mode"    = "THERMAL_DIODE"
 153                                         register "TMPIN2.mode"    = "THERMAL_DIODE"
 154
 155                                         register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU_FAN
 156                                         register "FAN3.mode" = "FAN_SMART_AUTOMATIC" # SYS_FAN
 157
 158                                         register "FAN2.smart.tmpin"     = "1"
 159                                         register "FAN2.smart.tmp_off"   = "35"
 160                                         register "FAN2.smart.tmp_start" = "42"
 161                                         register "FAN2.smart.tmp_full"  = "72"
 162                                         register "FAN2.smart.tmp_delta" = "2"
 163                                         register "FAN2.smart.pwm_start" = "26"
 164                                         register "FAN2.smart.slope"     = "24"
 165
 166                                         register "FAN3.smart.tmpin"     = "1"
 167                                         register "FAN3.smart.tmp_off"   = "35"
 168                                         register "FAN3.smart.tmp_start" = "42"
 169                                         register "FAN3.smart.tmp_full"  = "72"
 170                                         register "FAN3.smart.tmp_delta" = "2"
 171                                         register "FAN3.smart.pwm_start" = "26"
 172                                         register "FAN3.smart.slope"     = "24"
 173                                 end
 174
 175                                 device pnp 2e.5 off end
 176                                 device pnp 2e.6 off end
 177
 178                                 device pnp 2e.7 on      # GPIO
 179                                         irq 0x2d = 0x02
 180                                         io 0x60  = 0xa10
 181                                         io 0x62  = 0xa00
 182                                         irq 0x70 = 0x00
 183                                         irq 0x71 = 0x01
 184                                         irq 0xbc = 0xc0
 185                                         irq 0xbd = 0x03
 186                                         irq 0xc1 = 0x02
 187                                         irq 0xc8 = 0x00
 188                                         irq 0xc9 = 0x02
 189                                         irq 0xda = 0xb0
 190                                         irq 0xdb = 0x44
 191                                 end
 192                                 device pnp 2e.a off end # CIR
 193                         end
 194                 end
 195                 device ref p2sb hidden end
 196                 device ref hda on
 197                         subsystemid 0x10ec 0x3000
 198                         register "PchHdaAudioLinkHdaEnable" = "1"
 199                 end
 200                 device ref smbus on end
 201         end
 202         chip drivers/crb
 203                 device mmio 0xfed40000 on end
 204         end
 205 end