src/mainboard/erying/tgl/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/gpio.h>
   4
   5 static const struct pad_config gpio_table[] = {
   6
   7         /* ------- GPIO Community 0 ------- */
   8
   9         /* ------- GPIO Group GPP_A ------- */
  10         PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1),  // ESPI_IO0
  11         PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),  // ESPI_IO1
  12         PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),  // ESPI_IO2
  13         PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),  // ESPI_IO3
  14         PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),  // ESPI_CS0#
  15         PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1),  // ESPI_CLK
  16         PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1),  // ESPI_RESET#
  17         PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1),  // ESPI_CS1#
  18         PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),  // ESPI_CS2#
  19         PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),  // ESPI_CS3#
  20         PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALERT0#
  21         PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // ESPI_ALERT1#
  22         PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // ESPI_ALERT2#
  23         PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // ESPI_ALERT3#
  24         _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* n/a */
  25
  26         /* ------- GPIO Group GPP_R ------- */
  27         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),    // HDA_BITCLK
  28         PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),  // HDA_SYNC
  29         PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),  // HDA_SDOUT
  30         PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),  // HDA_SDIN0
  31         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),    // HDA_RST#
  32         PAD_NC(GPP_R5, NONE),
  33         _PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),   /* n/a */
  34         _PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),   /* n/a */
  35         _PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* n/a */
  36         PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1),  // PCIE_LNK_DOWN
  37         PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1), // ISH_UART0_RTS#
  38         PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1), // SX_EXIT_HOLDOFF#
  39         _PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* CLKOUT_48 */
  40         _PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* ISH_GP7 */
  41         PAD_NC(GPP_R14, NONE),
  42         PAD_NC(GPP_R15, NONE),
  43         PAD_NC(GPP_R16, NONE),
  44         PAD_NC(GPP_R17, NONE),
  45         PAD_CFG_GPO(GPP_R18, 1, PLTRST),        /* GPIO */
  46         PAD_NC(GPP_R19, NONE),
  47
  48         /* ------- GPIO Group GPP_B ------- */
  49         PAD_CFG_GPO(GPP_B0, 1, PLTRST), /* GPIO */
  50         PAD_NC(GPP_B1, NONE),
  51         PAD_NC(GPP_B2, NONE),
  52         PAD_NC(GPP_B3, NONE),
  53         PAD_NC(GPP_B4, NONE),
  54         PAD_NC(GPP_B5, NONE),
  55         PAD_NC(GPP_B6, NONE),
  56         PAD_NC(GPP_B7, NONE),
  57         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),    // SRCCLKREQ3
  58         PAD_NC(GPP_B9, NONE),
  59         PAD_NC(GPP_B10, NONE),
  60         PAD_CFG_GPO(GPP_B11, 1, DEEP),  /* GPIO */
  61         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),   // SLP_S0#
  62         PAD_NC(GPP_B13, NONE),
  63         PAD_NC(GPP_B14, NONE),
  64         PAD_NC(GPP_B15, NONE),
  65         PAD_NC(GPP_B16, NONE),
  66         PAD_NC(GPP_B17, NONE),
  67         PAD_NC(GPP_B18, NONE),
  68         PAD_NC(GPP_B19, NONE),
  69         _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* GSPI1_CLK */
  70         _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* GSPI1_MISO */
  71         _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),     /* GSPI1_MOSI */
  72         PAD_CFG_GPO(GPP_B23, 1, PLTRST),        /* GPIO */
  73
  74         /* ------- GPIO Community 1 ------- */
  75
  76         /* ------- GPIO Group GPP_D ------- */
  77         PAD_NC(GPP_D0, NONE),
  78         PAD_NC(GPP_D1, NONE),
  79         PAD_NC(GPP_D2, NONE),
  80         PAD_NC(GPP_D3, NONE),
  81         _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),      /* SML1CLK */
  82         _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CNV_RF_RESET# */
  83         _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* MODEM_CLKREQ */
  84         PAD_NC(GPP_D7, NONE),
  85         PAD_NC(GPP_D8, NONE),
  86         _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SML0CLK */
  87         _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),       /* SML0DATA */
  88         PAD_CFG_GPO(GPP_D11, 1, PLTRST),        /* GPIO */
  89         PAD_CFG_GPO(GPP_D12, 1, PLTRST),        /* GPIO */
  90         PAD_NC(GPP_D13, NONE),
  91         PAD_NC(GPP_D14, NONE),
  92         _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),     /* SML1DATA */
  93         PAD_NC(GPP_D16, NONE),
  94         PAD_NC(GPP_D17, NONE),
  95         PAD_NC(GPP_D18, NONE),
  96         PAD_NC(GPP_D19, NONE),
  97         PAD_NC(GPP_D20, NONE),
  98         PAD_NC(GPP_D21, NONE),
  99         PAD_NC(GPP_D22, NONE),
 100         PAD_NC(GPP_D23, NONE),
 101
 102         /* ------- GPIO Group GPP_C ------- */
 103         _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SMBCLK */
 104         _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SMBDATA */
 105         PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
 106         _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* I2C2_SDA */
 107         _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* I2C2_SCL */
 108         PAD_CFG_GPO(GPP_C5, 0, DEEP),   /* GPIO */
 109         _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* I2C3_SDA */
 110         _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* I2C3_SCL */
 111         PAD_NC(GPP_C8, NONE),
 112         PAD_NC(GPP_C9, NONE),
 113         PAD_NC(GPP_C10, NONE),
 114         PAD_NC(GPP_C11, NONE),
 115         PAD_CFG_GPO(GPP_C12, 1, PLTRST),        /* GPIO */
 116         PAD_CFG_GPO(GPP_C13, 1, PLTRST),        /* GPIO */
 117         PAD_CFG_GPO(GPP_C14, 1, PLTRST),        /* GPIO */
 118         PAD_CFG_GPO(GPP_C15, 1, PLTRST),        /* GPIO */
 119         _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* I2C0_SDA */
 120         _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* I2C0_SCL */
 121         _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* I2C1_SDA */
 122         _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* I2C1_SCL */
 123         PAD_NC(GPP_C20, NONE),
 124         PAD_NC(GPP_C21, NONE),
 125         PAD_NC(GPP_C22, NONE),
 126         PAD_NC(GPP_C23, NONE),
 127
 128         /* ------- GPIO Group GPP_S ------- */
 129         _PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* SNDW1_CLK */
 130         _PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* SNDW1_DATA */
 131         _PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* SNDW2_CLK */
 132         _PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* SNDW2_DATA */
 133         _PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DMIC_CLKA1 */
 134         _PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DMIC_DATA1 */
 135         _PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DMIC_CLKA0 */
 136         _PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DMIC_DATA0 */
 137
 138         /* ------- GPIO Group GPP_G ------- */
 139         PAD_NC(GPP_G0, NONE),
 140         PAD_CFG_GPO(GPP_G1, 0, DEEP),   /* GPIO */
 141         PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* GPIO */
 142         PAD_CFG_GPO(GPP_G3, 1, PLTRST), /* GPIO */
 143         PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* GPIO */
 144         _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* SLP_DRAM# */
 145         PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* GPIO */
 146         PAD_CFG_GPO(GPP_G7, 1, PLTRST), /* GPIO */
 147         _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),    /* DDP3_CTRLCLK */
 148         _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),    /* DDP3_CTRLDATA */
 149         _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP4_CTRLCLK */
 150         _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP4_CTRLDATA */
 151         _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP1_CTRLCLK */
 152         _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP1_CTRLDATA */
 153         _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP2_CTRLCLK */
 154         _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),   /* DDP2_CTRLDATA */
 155
 156         /* ------- GPIO Community 2 ------- */
 157
 158         /* ------- GPIO Group GPD ------- */
 159         PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),   /* BATLOW# */
 160         PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),   /* ACPRESENT */
 161         PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),   /* LAN_WAKE# */
 162         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),   /* PWRBTN# */
 163         PAD_CFG_NF(GPD4, NONE, PWROK, NF1),     /* SLP_S3# */
 164         PAD_CFG_NF(GPD5, NONE, PWROK, NF1),     /* SLP_S4# */
 165         PAD_CFG_NF(GPD6, NONE, PWROK, NF1),     /* SLP_A# */
 166         PAD_CFG_GPO(GPD7, 0, PWROK),            /* GPIO */
 167         PAD_CFG_NF(GPD8, NONE, PWROK, NF1),     /* SUSCLK */
 168         PAD_CFG_NF(GPD9, NONE, PWROK, NF1),     /* SLP_WLAN# */
 169         PAD_CFG_NF(GPD10, NONE, PWROK, NF1),    /* SLP_S5# */
 170         PAD_CFG_NF(GPD11, NONE, PWROK, NF1),    /* LANPHYPC */
 171         PAD_NC(GPD12, NONE),                    /* GPIO */
 172
 173         /* ------- GPIO Community 3 ------- */
 174
 175         /* ------- GPIO Group GPP_E ------- */
 176         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),    /* SATAXPCIE0 */
 177         PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),  /* SATAXPCIE1 */
 178         PAD_CFG_GPO(GPP_E2, 1, PLTRST),         /* GPIO */
 179         PAD_CFG_GPO(GPP_E3, 1, PLTRST),         /* GPIO */
 180         PAD_CFG_GPO(GPP_E4, 1, PLTRST),         /* SATA_DEVSLP0 */
 181         PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1),  /* SATA_DEVSLP1 */
 182         PAD_CFG_GPO(GPP_E6, 1, PLTRST),         /* GPIO */
 183         PAD_NC(GPP_E7, NONE),
 184         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),    /* SATALED# */
 185         PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),  /* USB_OC0# */
 186         PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), /* USB_OC1# */
 187         PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), /* USB_OC2# */
 188         PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), /* USB_OC3# */
 189
 190         /* ------- GPIO Group GPP_F ------- */
 191         _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SATAXPCIE3 */
 192         _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SATAXPCIE4 */
 193         _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* SATAXPCIE5 */
 194         PAD_CFG_GPO(GPP_F3, 0, PLTRST),         /* GPIO */
 195         PAD_CFG_GPO(GPP_F4, 1, PLTRST),         /* GPIO */
 196         PAD_CFG_GPO(GPP_F5, 1, PLTRST),         /* GPIO */
 197         PAD_NC(GPP_F6, NONE),
 198         PAD_CFG_GPO(GPP_F7, 1, PLTRST),         /* GPIO */
 199         PAD_NC(GPP_F8, NONE),
 200         PAD_CFG_GPO(GPP_F9, 1, PLTRST),         /* GPIO */
 201         PAD_NC(GPP_F10, NONE),
 202         PAD_CFG_GPO(GPP_F11, 1, PLTRST),        /* GPIO */
 203         PAD_CFG_GPO(GPP_F12, 1, DEEP),          /* GPIO */
 204         PAD_CFG_GPO(GPP_F13, 1, PLTRST),        /* GPIO */
 205         PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), /* PS_ON# */
 206         PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),   /* GPIO */
 207         PAD_CFG_GPO(GPP_F16, 1, PLTRST),        /* GPIO */
 208         PAD_NC(GPP_F17, NONE),
 209         PAD_CFG_GPO(GPP_F18, 1, PLTRST),        /* GPIO */
 210         _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* eDP_VDDEN */
 211         _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* eDP_BKLTEN */
 212         _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),  /* eDP_BKLTCTL */
 213         PAD_NC(GPP_F22, NONE),
 214         PAD_CFG_GPO(GPP_F23, 1, PLTRST),        /* GPIO */
 215
 216         /* ------- GPIO Community 4 ------- */
 217
 218         /* ------- GPIO Group GPP_H ------- */
 219         PAD_NC(GPP_H0, NONE),
 220         PAD_NC(GPP_H1, NONE),
 221         PAD_NC(GPP_H2, NONE),
 222         PAD_NC(GPP_H3, NONE),
 223         PAD_NC(GPP_H4, NONE),
 224         PAD_NC(GPP_H5, NONE),
 225         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),    // SRCCLKREQ12
 226         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),    // SRCCLKREQ13
 227         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),    // SRCCLKREQ14
 228         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),    // SRCCLKREQ15
 229         PAD_CFG_GPO(GPP_H10, 1, PLTRST),        // GPIO */
 230         PAD_NC(GPP_H11, NONE),
 231         PAD_CFG_GPO(GPP_H12, 1, PLTRST),        /* GPIO */
 232         PAD_CFG_GPO(GPP_H13, 1, PLTRST),        /* GPIO */
 233         PAD_CFG_GPO(GPP_H14, 0, PLTRST),        /* GPIO */
 234         PAD_CFG_GPO(GPP_H15, 1, PLTRST),        /* GPIO */
 235         PAD_CFG_GPO(GPP_H16, 1, PLTRST),        /* GPIO */
 236         PAD_CFG_GPO(GPP_H17, 1, PLTRST),        /* GPIO */
 237         PAD_CFG_GPO(GPP_H18, 0, PLTRST),        /* GPIO */
 238         PAD_NC(GPP_H19, NONE),
 239         PAD_NC(GPP_H20, NONE),
 240         PAD_NC(GPP_H21, NONE),
 241         PAD_NC(GPP_H22, NONE),
 242         PAD_CFG_GPO(GPP_H23, 1, PLTRST),        /* GPIO */
 243
 244         /* ------- GPIO Group GPP_J ------- */
 245         PAD_CFG_GPO(GPP_J0, 1, PLTRST), /* GPIO */
 246         _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CPU_C10_GATE# */
 247         _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CNV_BRI_DT */
 248         _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */
 249         _PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CNV_RGI_DT */
 250         _PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */
 251         PAD_NC(GPP_J6, NONE),
 252         PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI),  /* GPIO */
 253         PAD_CFG_GPO(GPP_J8, 1, PLTRST), /* GPIO */
 254         PAD_CFG_GPO(GPP_J9, 1, PLTRST), /* GPIO */
 255
 256         /* ------- GPIO Group GPP_K ------- */
 257         PAD_CFG_GPO(GPP_K0, 1, PLTRST), /* GPIO */
 258         PAD_CFG_GPO(GPP_K1, 1, PLTRST), /* GPIO */
 259         PAD_CFG_GPO(GPP_K2, 1, PLTRST), /* GPIO */
 260         PAD_CFG_GPO(GPP_K3, 1, PLTRST), /* GPIO */
 261         PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
 262         PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
 263         _PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDSP_HPDA */
 264         _PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDSP_HPDB */
 265         _PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CORE_VID0 */
 266         _PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* CORE_VID1 */
 267         PAD_CFG_GPO(GPP_K10, 1, PLTRST),        /* GPIO */
 268         PAD_NC(GPP_K11, NONE),
 269
 270         /* ------- GPIO Community 5 ------- */
 271
 272         /* ------- GPIO Group GPP_I ------- */
 273         _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),      /* PMCALERT# */
 274         _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDSP_HPD1 */
 275         _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),        /* DDSP_HPD2 */
 276         _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDSP_HPD3 */
 277         _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDSP_HPD4 */
 278         _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),   /* DDPB_CTRLCLK */
 279         _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),      /* DDPB_CTRLDATA */
 280         PAD_NC(GPP_I7, NONE),
 281         PAD_CFG_GPO(GPP_I8, 1, PLTRST), /* GPIO */
 282         PAD_CFG_GPO(GPP_I9, 1, PLTRST), /* GPIO */
 283         PAD_CFG_GPO(GPP_I10, 1, PLTRST),        /* GPIO */
 284         _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),       /* I2C4_SDA */
 285         _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),       /* I2C4_SCL */
 286         _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),       /* USB_OC6# */
 287         _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),       /* I2C5_SCL */
 288 };