mb/google/brya: Create rull variant

[coreboot2.git] / src / mainboard / google / cyan / variants / ultima / overridetree.cb

chip soc/intel/braswell

        register "PcdEnableI2C0" = "1"          # Touchscreen

        register "PcdPchSsicEnable" = "0"
        register "PcdPchUsbHsicPort" = "0"

        device domain 0 on
                device pci 18.1 on  end # 8086 22c1 - I2C Port 1: Touchscreen
        end
end