src/mainboard/google/fizz/variants/endeavour/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6
   7 /* Pad configuration in ramstage */
   8 /* Leave eSPI pins untouched from default settings */
   9 static const struct pad_config gpio_table[] = {
  10 /* RCIN# */             PAD_NC(GPP_A0, NONE), /* TP308 */
  11 /* ESPI_IO0 */
  12 /* ESPI_IO1 */
  13 /* ESPI_IO2 */
  14 /* ESPI_IO3 */
  15 /* ESPI_CS# */
  16 /* SERIRQ */            PAD_NC(GPP_A6, NONE), /* TP331 */
  17 /* PIRQA# */            PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), /* SD_CDZ */
  18 /* CLKRUN# */           PAD_NC(GPP_A8, NONE), /* TP329 */
  19 /* ESPI_CLK */
  20 /* CLKOUT_LPC1 */       PAD_NC(GPP_A10, NONE), /* TP188 */
  21 /* PME# */              PAD_NC(GPP_A11, NONE), /* TP149 */
  22 /* BM_BUSY# */          PAD_NC(GPP_A12, NONE),
  23 /* SUSWARN# */          PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */
  24 /* ESPI_RESET# */
  25 /* SUSACK# */           PAD_NC(GPP_A15, NONE), /* TP150 */
  26 /* SD_1P8_SEL */        PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  27 /* SD_PWR_EN# */        PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  28 /* ISH_GP0 */           PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */
  29 /* ISH_GP1 */           PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
  30 /* ISH_GP2 */           PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */
  31 /* ISH_GP3 */           PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */
  32 /* ISH_GP4 */           PAD_NC(GPP_A22, NONE),
  33 /* ISH_GP5 */           PAD_NC(GPP_A23, NONE),
  34
  35 /* CORE_VID0 */         PAD_NC(GPP_B0, NONE), /* TP156 */
  36 /* CORE_VID1 */         PAD_NC(GPP_B1, NONE),
  37 /* VRALERT# */          PAD_NC(GPP_B2, NONE), /* TP152 */
  38 /* CPU_GP2 */           PAD_NC(GPP_B3, NONE),
  39 /* CPU_GP3 */           PAD_NC(GPP_B4, NONE),
  40 /* SRCCLKREQ0# */       PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */
  41 /* SRCCLKREQ1# */       PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */
  42 /* SRCCLKREQ2# */       PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */
  43 /* SRCCLKREQ3# */       PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* PCIE_CLKREQ_POE# */
  44 /* SRCCLKREQ4# */       PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU1# */
  45 /* SRCCLKREQ5# */       PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */
  46 /* EXT_PWR_GATE# */     PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
  47 /* SLP_S0# */           PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
  48 /* PLTRST# */           PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
  49 /* SPKR */              PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
  50 /* GSPI0_CS# */         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */
  51 /* GSPI0_CLK */         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */
  52 /* GSPI0_MISO */        PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */
  53 /* GSPI0_MOSI */        PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */
  54 /* GSPI1_CS# */         PAD_NC(GPP_B19, NONE), /* TP98 */
  55 /* GSPI1_CLK */         PAD_NC(GPP_B20, NONE),
  56 /* GSPI1_MISO */        PAD_NC(GPP_B21, NONE),
  57 /* GSPI1_MOSI */        PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */
  58 /* SML1ALERT# */        PAD_NC(GPP_B23, NONE), /* TP44 */
  59
  60 /* SMBCLK */            PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
  61 /* SMBDATA */           PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
  62 /* SMBALERT# */         PAD_NC(GPP_C2, NONE),
  63 /* SML0CLK */           PAD_NC(GPP_C3, NONE),
  64 /* SML0DATA */          PAD_NC(GPP_C4, NONE),
  65 /* SML0ALERT# */        PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
  66 /* SM1CLK */            PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */
  67 /* SM1DATA */           PAD_NC(GPP_C7, NONE), /* TP99 */
  68 /* UART0_RXD */         PAD_NC(GPP_C8, NONE),
  69 /* UART0_TXD */         PAD_NC(GPP_C9, NONE),
  70 /* UART0_RTS# */        PAD_NC(GPP_C10, NONE),
  71 /* UART0_CTS# */        PAD_NC(GPP_C11, NONE),
  72 /* UART1_RXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */
  73 /* UART1_TXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */
  74 /* UART1_RTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */
  75 /* UART1_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */
  76 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */
  77 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */
  78 /* I2C1_SDA */          PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */
  79 /* I2C1_SCL */          PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */
  80 /* UART2_RXD */         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
  81 /* UART2_TXD */         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
  82 /* UART2_RTS# */        PAD_NC(GPP_C22, NONE), /* TP93 */
  83 /* UART2_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */
  84
  85 /* SPI1_CS# */          PAD_NC(GPP_D0, NONE), /* TP106 */
  86 /* SPI1_CLK */          PAD_NC(GPP_D1, NONE), /* TP102 */
  87 /* SPI1_MISO */         PAD_NC(GPP_D2, NONE), /* TP104 */
  88 /* SPI1_MOSI */         PAD_NC(GPP_D3, NONE), /* TP105 */
  89 /* FASHTRIG */          PAD_NC(GPP_D4, NONE), /* TP91 */
  90 /* ISH_I2C0_SDA */      PAD_NC(GPP_D5, NONE),
  91 /* ISH_I2C0_SCL */      PAD_NC(GPP_D6, NONE),
  92 /* ISH_I2C1_SDA */      PAD_NC(GPP_D7, NONE),
  93 /* ISH_I2C1_SCL */      PAD_NC(GPP_D8, NONE),
  94 /* ISH_SPI_CS# */       PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */
  95 /* ISH_SPI_CLK */       PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */
  96 /* ISH_SPI_MISO */      PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */
  97 /* ISH_SPI_MOSI */      PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */
  98 /* ISH_UART0_RXD */     PAD_NC(GPP_D13, NONE),
  99 /* ISH_UART0_TXD */     PAD_NC(GPP_D14, NONE),
 100 /* ISH_UART0_RTS# */    PAD_NC(GPP_D15, NONE),
 101 /* ISH_UART0_CTS# */    PAD_NC(GPP_D16, NONE),
 102 /* DMIC_CLK1 */         PAD_NC(GPP_D17, NONE),
 103 /* DMIC_DATA1 */        PAD_NC(GPP_D18, NONE),
 104 /* DMIC_CLK0 */         PAD_NC(GPP_D19, NONE), /* TP100 */
 105 /* DMIC_DATA0 */        PAD_NC(GPP_D20, NONE), /* TP90 */
 106 /* SPI1_IO2 */          PAD_NC(GPP_D21, NONE), /* TP101 */
 107 /* SPI1_IO3 */          PAD_NC(GPP_D22, NONE), /* TP94 */
 108 /* I2S_MCLK */          PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
 109
 110 /* SATAXPCI0 */         PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */
 111 /* SATAXPCIE1 */        PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */
 112 /* SATAXPCIE2 */        PAD_NC(GPP_E2, NONE),
 113 /* CPU_GP0 */           PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP,
 114                                            NONE), /* TPU_RST_PIN40 */
 115 /* SATA_DEVSLP0 */      PAD_NC(GPP_E4, NONE), /* TP103 */
 116 /* SATA_DEVSLP1 */      PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
 117 /* SATA_DEVSLP2 */      PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */
 118 /* CPU_GP1 */           PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP,
 119                                            NONE), /* TPU_RST_PIN42 */
 120 /* SATALED# */          PAD_NC(GPP_E8, NONE), /* TP96 */
 121 /* USB2_OCO# */         PAD_NC(GPP_E9, NONE), /* T1037 */
 122 /* USB2_OC1# */         PAD_NC(GPP_E10, NONE), /* T1025 */
 123 /* USB2_OC2# */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */
 124 /* USB2_OC3# */         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */
 125 /* DDPB_HPD0 */         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */
 126 /* DDPC_HPD1 */         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */
 127 /* DDPD_HPD2 */         PAD_CFG_GPI_APIC_HIGH(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */
 128 /* DDPE_HPD3 */         PAD_NC(GPP_E16, NONE), /* TP1021 */
 129 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 130 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */
 131 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */
 132 /* DDPC_CTRLCLK */      PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */
 133 /* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */
 134 /* DDPD_CTRLCLK */      PAD_NC(GPP_E22, NONE),
 135 /* DDPD_CTRLDATA */     PAD_NC(GPP_E23, NONE),
 136
 137 /* I2S2_SCLK */         PAD_NC(GPP_F0, NONE), /* TP43 */
 138 /* I2S2_SFRM */         PAD_NC(GPP_F1, NONE), /* TP48 */
 139 /* I2S2_TXD */          PAD_NC(GPP_F2, NONE), /* TP42 */
 140 /* I2S2_RXD */          PAD_NC(GPP_F3, NONE), /* TP37 */
 141 /* I2C2_SDA */          PAD_NC(GPP_F4, NONE),
 142 /* I2C2_SCL */          PAD_NC(GPP_F5, NONE),
 143 /* I2C3_SDA */          PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */
 144 /* I2C3_SCL */          PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */
 145 /* I2C4_SDA */          PAD_NC(GPP_F8, NONE),
 146 /* I2C4_SCL */          PAD_NC(GPP_F9, NONE),
 147 /* I2C5_SDA */          PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
 148 /* I2C5_SCL */          PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
 149 /* EMMC_CMD */          PAD_NC(GPP_F12, NONE),
 150 /* EMMC_DATA0 */        PAD_NC(GPP_F13, NONE),
 151 /* EMMC_DATA1 */        PAD_NC(GPP_F14, NONE),
 152 /* EMMC_DATA2 */        PAD_NC(GPP_F15, NONE),
 153 /* EMMC_DATA3 */        PAD_NC(GPP_F16, NONE),
 154 /* EMMC_DATA4 */        PAD_NC(GPP_F17, NONE),
 155 /* EMMC_DATA5 */        PAD_NC(GPP_F18, NONE),
 156 /* EMMC_DATA6 */        PAD_NC(GPP_F19, NONE),
 157 /* EMMC_DATA7 */        PAD_NC(GPP_F20, NONE),
 158 /* EMMC_RCLK */         PAD_NC(GPP_F21, NONE),
 159 /* EMMC_CLK */          PAD_NC(GPP_F22, NONE),
 160 /* RSVD */              PAD_NC(GPP_F23, NONE),
 161
 162 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 163 /* SD_DATA0 */          PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 164 /* SD_DATA1 */          PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 165 /* SD_DATA2 */          PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 166 /* SD_DATA3 */          PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 167 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
 168 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 169 /* SD_WP */             PAD_NC(GPP_G7, NONE), /* TP40 */
 170
 171 /* BATLOW# */           PAD_NC(GPD0, NONE), /* TP23 */
 172 /* ACPRESENT */         PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
 173 /* LAN_WAKE# */         PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
 174 /* PWRBTN# */           PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */
 175 /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
 176 /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
 177 /* SLP_A# */            PAD_NC(GPD6, NONE), /* TP22 */
 178 /* RSVD */              PAD_NC(GPD7, NONE),
 179 /* SUSCLK */            PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
 180 /* SLP_WLAN# */         PAD_NC(GPD9, NONE), /* TP83 */
 181 /* SLP_S5# */           PAD_NC(GPD10, NONE), /* TP84 */
 182 /* LANPHYC */           PAD_NC(GPD11, NONE),
 183 };
 184
 185 const struct pad_config *variant_gpio_table(size_t *num)
 186 {
 187         *num = ARRAY_SIZE(gpio_table);
 188         return gpio_table;
 189 }