mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / google / reef / variants / baseboard / devicetree.cb
blob1192a5f23207314bff7dd4e01dca31f3b8f5dc49
1 chip soc/intel/apollolake
3 register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
4 # Disable unused clkreq of PCIe root ports
5 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
6 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
7 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
8 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
9 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
11 # GPIO for PERST_0
12 # If the Board has PERST_0 signal, assign the GPIO
13 # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
14 register "prt0_gpio" = "GPIO_122"
16 # GPIO for SD card detect
17 register "sdcard_cd_gpio" = "GPIO_177"
19 # EMMC TX DATA Delay 1
20 # Refer to EDS-Vol2-22.3.
21 # [14:8] steps of delay for HS400, each 125ps.
22 # [6:0] steps of delay for SDR104/HS200, each 125ps.
23 register "emmc_tx_data_cntl1" = "0x0C16"
25 # EMMC TX DATA Delay 2
26 # Refer to EDS-Vol2-22.3.
27 # [30:24] steps of delay for SDR50, each 125ps.
28 # [22:16] steps of delay for DDR50, each 125ps.
29 # [14:8] steps of delay for SDR25/HS50, each 125ps.
30 # [6:0] steps of delay for SDR12, each 125ps.
31 register "emmc_tx_data_cntl2" = "0x28162828"
33 # EMMC RX CMD/DATA Delay 1
34 # Refer to EDS-Vol2-22.3.
35 # [30:24] steps of delay for SDR50, each 125ps.
36 # [22:16] steps of delay for DDR50, each 125ps.
37 # [14:8] steps of delay for SDR25/HS50, each 125ps.
38 # [6:0] steps of delay for SDR12, each 125ps.
39 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
41 # EMMC RX CMD/DATA Delay 2
42 # Refer to EDS-Vol2-22.3.
43 # [17:16] stands for Rx Clock before Output Buffer
44 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
45 # [6:0] steps of delay for HS200, each 125ps.
46 register "emmc_rx_cmd_data_cntl2" = "0x10008"
48 # Enable DPTF
49 register "dptf_enable" = "1"
51 # PL1 override 12 W: the energy calculation is wrong with the
52 # current VR solution. Experiments show that SoC TDP max (6W) can
53 # be reached when RAPL PL1 is set to 12W.
54 # Set RAPL PL2 to 15W.
55 register "power_limits_config" = "{
56 .tdp_pl1_override = 12,
57 .tdp_pl2_override = 15,
60 # Enable Audio Clock and Power gating
61 register "hdaudio_clk_gate_enable" = "1"
62 register "hdaudio_pwr_gate_enable" = "1"
63 register "hdaudio_bios_config_lockdown" = "1"
65 # Enable lpss s0ix
66 register "lpss_s0ix_enable" = "true"
68 # GPE configuration
69 # Note that GPE events called out in ASL code rely on this
70 # route, i.e., if this route changes then the affected GPE
71 # offset bits also need to be changed. This sets the PMC register
72 # GPE_CFG fields.
73 register "gpe0_dw1" = "PMC_GPE_N_31_0"
74 register "gpe0_dw2" = "PMC_GPE_N_63_32"
75 register "gpe0_dw3" = "PMC_GPE_SW_31_0"
77 # Intel Common SoC Config
78 #+-------------------+---------------------------+
79 #| Field | Value |
80 #+-------------------+---------------------------+
81 #| I2C0 | Audio |
82 #| I2C2 | TPM |
83 #| I2C3 | Touchscreen |
84 #| I2C4 | Trackpad |
85 #| I2C5 | Digitizer |
86 #+-------------------+---------------------------+
87 register "common_soc_config" = "{
88 .i2c[0] = {
89 .speed = I2C_SPEED_FAST,
90 .rise_time_ns = 104,
91 .fall_time_ns = 52,
93 .i2c[2] = {
94 .early_init = 1,
95 .speed = I2C_SPEED_FAST,
96 .rise_time_ns = 57,
97 .fall_time_ns = 28,
99 .i2c[3] = {
100 .speed = I2C_SPEED_FAST,
101 .rise_time_ns = 76,
102 .fall_time_ns = 164,
104 .i2c[4] = {
105 .speed = I2C_SPEED_FAST,
106 .rise_time_ns = 114,
107 .fall_time_ns = 164,
108 .data_hold_time_ns = 350,
110 .i2c[5] = {
111 .speed = I2C_SPEED_FAST,
112 .rise_time_ns = 152,
113 .fall_time_ns = 30,
117 # Minimum SLP S3 assertion width 28ms.
118 register "slp_s3_assertion_width_usecs" = "28000"
120 device domain 0 on
121 device pci 00.0 on end # - Host Bridge
122 device pci 00.1 on end # - DPTF
123 device pci 00.2 off end # - NPK
124 device pci 02.0 on # - Gen
125 register "gfx" = "GMA_DEFAULT_PANEL(0)"
127 device pci 03.0 off end # - Iunit
128 device pci 0d.0 on end # - P2SB
129 device pci 0d.1 on end # - PMC
130 device pci 0d.2 on end # - SPI
131 device pci 0d.3 on end # - Shared SRAM
132 device pci 0e.0 on # - Audio
133 chip drivers/generic/max98357a
134 register "hid" = ""MX98357A""
135 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
136 register "sdmode_delay" = "5"
137 device generic 0 on end
140 device pci 0f.0 on end # - CSE
141 device pci 11.0 off end # - ISH
142 device pci 12.0 off end # - SATA
143 device pci 13.0 off end # - Root Port 2 - PCIe-A 0
144 device pci 13.1 off end # - Root Port 3 - PCIe-A 1
145 device pci 13.2 off end # - Root Port 4 - PCIe-A 2
146 device pci 13.3 off end # - Root Port 5 - PCIe-A 3
147 device pci 14.0 on
148 chip drivers/wifi/generic
149 register "wake" = "GPE0_DW3_00"
150 device pci 00.0 on end
152 end # - Root Port 0 - PCIe-B 0 - Wifi
153 device pci 14.1 off end # - Root Port 1 - PCIe-B 1
154 device pci 15.0 on end # - XHCI
155 device pci 15.1 off end # - XDCI
156 device pci 16.0 on # - I2C 0
157 chip drivers/i2c/da7219
158 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
159 register "btn_cfg" = "50"
160 register "mic_det_thr" = "200"
161 register "jack_ins_deb" = "20"
162 register "jack_det_rate" = ""32ms_64ms""
163 register "jack_rem_deb" = "1"
164 register "a_d_btn_thr" = "0xa"
165 register "d_b_btn_thr" = "0x16"
166 register "b_c_btn_thr" = "0x21"
167 register "c_mic_btn_thr" = "0x3e"
168 register "btn_avg" = "4"
169 register "adc_1bit_rpt" = "1"
170 register "micbias_lvl" = "2600"
171 register "mic_amp_in_sel" = ""diff""
172 device i2c 1a on end
175 device pci 16.1 on end # - I2C 1
176 device pci 16.2 on
177 chip drivers/i2c/tpm
178 register "hid" = ""GOOG0005""
179 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
180 device i2c 50 on end
182 end # - I2C 2
183 device pci 16.3 on
184 chip drivers/i2c/generic
185 register "hid" = ""ELAN0001""
186 register "desc" = ""ELAN Touchscreen""
187 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
188 register "detect" = "1"
189 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
190 register "reset_delay_ms" = "20"
191 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
192 register "enable_delay_ms" = "1"
193 register "has_power_resource" = "1"
194 device i2c 10 on end
196 end # - I2C 3
197 device pci 17.0 on
198 chip drivers/i2c/generic
199 register "hid" = ""ELAN0000""
200 register "desc" = ""ELAN Touchpad""
201 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
202 register "wake" = "GPE0_DW1_15"
203 register "detect" = "1"
204 device i2c 15 on end
206 end # - I2C 4
207 device pci 17.1 on
208 chip drivers/i2c/hid
209 register "generic.hid" = ""WCOM50C1""
210 register "generic.desc" = ""WCOM Digitizer""
211 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
212 register "hid_desc_reg_offset" = "0x1"
213 device i2c 0x9 on end
215 end # - I2C 5
216 device pci 17.2 off end # - I2C 6
217 device pci 17.3 off end # - I2C 7
218 device pci 18.0 on end # - UART 0
219 device pci 18.1 on end # - UART 1
220 device pci 18.2 on end # - UART 2
221 device pci 18.3 off end # - UART 3
222 device pci 19.0 on end # - SPI 0
223 device pci 19.1 off end # - SPI 1
224 device pci 19.2 off end # - SPI 2
225 device pci 1a.0 on end # - PWM
226 device pci 1b.0 on end # - SDCARD
227 device pci 1c.0 on end # - eMMC
228 device pci 1e.0 off end # - SDIO
229 device pci 1f.0 on # - LPC
230 chip ec/google/chromeec
231 device pnp 0c09.0 on end
234 device pci 1f.1 on end # - SMBUS