src/mainboard/google/rex/variants/ovis/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /* This header block is used to supply information to arbitrage, a
   4  * google-internal tool. Updating it incorrectly will lead to issues,
   5  * so please don't update it unless a change is specifically required.
   6  * BaseID: 3EC4CE58201758F4
   7  * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff
   8  */
   9
  10 #include <baseboard/gpio.h>
  11 #include <baseboard/variants.h>
  12 #include <soc/gpio.h>
  13 #include <boardid.h>
  14
  15 /* Pad configuration in ramstage */
  16 static const struct pad_config gpio_table[] = {
  17         /* GPP_A00 : [] ==> ESPI_SOC_IO0_R */
  18         PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE),
  19         /* GPP_A01 : [] ==> ESPI_SOC_IO1_R */
  20         PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE),
  21         /* GPP_A02 : [] ==> ESPI_SOC_IO2_R */
  22         PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE),
  23         /* GPP_A03 : [] ==> ESPI_SOC_IO3_R */
  24         PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE),
  25         /* GPP_A04 : [] ==> ESPI_SOC_CS0_L */
  26         PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE),
  27         /* GPP_A05 : [] ==> ESPI_SOC_CLK_R */
  28         PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE),
  29         /* GPP_A06 : [] ==> ESPI_SOC_RESET_L */
  30         PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE),
  31         /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */
  32         PAD_NC(GPP_A11, NONE),
  33         /* GPP_A12 : [] ==> EN_UCAM_PWR */
  34         PAD_NC(GPP_A12, NONE),
  35         /* GPP_A13 : [] ==> SD_PE_PRSNT_L */
  36         PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG),
  37         /* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */
  38         PAD_NC(GPP_A14, NONE),
  39         /* GPP_A15 : [] ==> WWAN_RST_L */
  40         PAD_NC(GPP_A15, NONE),
  41         /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */
  42         PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE),
  43         /* GPP_A17 : [] ==> EC_SOC_INT_ODL */
  44         PAD_CFG_GPI_IRQ_WAKE(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
  45         /* GPP_A18 : [] ==> CAM_PSW_L */
  46         PAD_NC(GPP_A18, NONE),
  47         /* GPP_A21 : [] ==> WWAN_CONFIG2 */
  48         PAD_NC(GPP_A21, NONE),
  49
  50         /* GPP_B00 : [] ==> TCHPAD_INT_ODL */
  51         PAD_NC(GPP_B00, NONE),
  52         /* GPP_B01 : [] ==> BT_DISABLE_L */
  53         PAD_CFG_GPO(GPP_B01, 1, DEEP),
  54         /* GPP_B02 : [] ==> SOC_ISH_I2C_SENSOR_SDA */
  55         PAD_CFG_NF_LOCK(GPP_B02, NONE, NF3, LOCK_CONFIG),
  56         /* GPP_B03 : [] ==> SOC_ISH_I2C_SENSOR_SCL */
  57         PAD_CFG_NF_LOCK(GPP_B03, NONE, NF3, LOCK_CONFIG),
  58         /* GPP_B04 : [] ==> GPP_B04_STRAP */
  59         PAD_NC(GPP_B04, NONE),
  60         /* GPP_B05 : [] ==> SPKR_INT_L_R */
  61         PAD_CFG_GPI(GPP_B05, NONE, DEEP),
  62         /* GPP_B06 : [] ==> HP_INT_L_R */
  63         PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH),
  64         /* GPP_B07 : [] ==> RST_HP_L */
  65         PAD_CFG_GPO(GPP_B07, 1, DEEP),
  66         /* GPP_B08 : [] ==> PWM_BUZZER */
  67         PAD_CFG_GPO(GPP_B08, 0, DEEP),
  68         /* GPP_B09 : [] ==> GPP_B09 */
  69         PAD_NC(GPP_B09, NONE),
  70         /* GPP_B10 : [] ==> WIFI_DISABLE_L */
  71         PAD_CFG_GPO(GPP_B10, 1, DEEP),
  72         /* GPP_B11 : [] ==> EN_FP_PWR */
  73         PAD_NC(GPP_B11, NONE),
  74         /* GPP_B12 : [] ==> SLP_S0_R_L */
  75         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  76         /* GPP_B13 : [] ==> PLT_RST_L */
  77         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  78         /* GPP_B14 : [] ==> GPP_B14_STRAP */
  79         PAD_NC(GPP_B14, NONE),
  80         /* GPP_B15 : [] ==> USB_A_OC_ODL */
  81         PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG),
  82         /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
  83         PAD_NC(GPP_B16, NONE),
  84         /* GPP_B17 : [] ==> EN_WWAN_RAILS */
  85         PAD_NC(GPP_B17, NONE),
  86         /* GPP_B18 : [] ==> I2C4_SDA */
  87         PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG),
  88         /* GPP_B19 : [] ==> I2C4_SCL */
  89         PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG),
  90         /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */
  91         PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG),
  92         /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */
  93         PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG),
  94         /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */
  95         PAD_CFG_GPO(GPP_B22, 0, DEEP),
  96         /* GPP_B23 : [] ==> WWAN_CONFIG */
  97         PAD_NC(GPP_B23, NONE),
  98
  99         /* GPP_C00 : [] ==> EN_TCHSCR_RAILS */
 100         PAD_NC(GPP_C00, NONE),
 101         /* GPP_C01 : [] ==> SOC_TCHSCR_RST_ODL */
 102         PAD_NC(GPP_C01, NONE),
 103         /* GPP_C02 : [] ==> SOC_TCHSCR_SPI_INT_STRAP */
 104         PAD_NC(GPP_C02, NONE),
 105         /* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */
 106         PAD_NC(GPP_C03, NONE),
 107         /* GPP_C04 : [] ==> EN_WCAM_PWR */
 108         PAD_NC(GPP_C04, NONE),
 109         /* GPP_C05 : [] ==> WWAN_PERST_L */
 110         PAD_NC(GPP_C05, NONE),
 111         /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */
 112         PAD_NC(GPP_C06, NONE),
 113         /* GPP_C07 : [] ==> SOC_TCHSCR_INT_L */
 114         PAD_NC(GPP_C07, NONE),
 115         /* GPP_C08 : [] ==> SOCHOT_ODL */
 116         PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2),
 117         /* GPP_C09 : [] ==> MISC_SYNC_IN */
 118         PAD_NC(GPP_C09, NONE),
 119         /* GPP_C10 : [] ==> EN_LAN_RAILS */
 120         PAD_CFG_GPO(GPP_C10, 1, DEEP),
 121         /* GPP_C11 : [] ==> SD_CLKREQ_ODL */
 122         PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
 123         /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */
 124         PAD_NC(GPP_C12, NONE),
 125         /* GPP_C13 : [] ==> LAN_PERST_L */
 126         PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG),
 127         /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */
 128         PAD_NC(GPP_C15, NONE),
 129         /* GPP_C16 : [] ==> USB_C0_LSX_TX */
 130         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 131         /* GPP_C17 : [] ==> USB_C0_LSX_RX */
 132         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 133         /* GPP_C18 : [] ==> USB_C1_LSX_TX */
 134         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 135         /* GPP_C19 : [] ==> USB_C1_LSX_RX */
 136         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 137         /* GPP_C20 : [] ==> USB_C2_LSX_TX */
 138         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 139         /* GPP_C21 : [] ==> USB_C2_LSX_RX */
 140         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 141         /* GPP_C22 : [] ==> SOC_FPMCU_BOOT0 */
 142         PAD_NC(GPP_C22, NONE),
 143         /* GPP_C23 : [] ==> SOC_FPMCU_RST_ODL */
 144         PAD_NC(GPP_C23, NONE),
 145
 146         /* GPP_D00 : [] ==> WCAM_MCLK_R */
 147         PAD_NC(GPP_D00, NONE),
 148         /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */
 149         PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG),
 150         /* GPP_D02 : [] ==> SD_PERST_L */
 151         PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG),
 152         /* GPP_D03 : [] ==> EN_SD_RAILS */
 153         PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG),
 154         /* GPP_D04 : [] ==> EN_SPKR */
 155         PAD_CFG_GPO(GPP_D04, 1, DEEP),
 156         /* GPP_D05 : [] ==> SPARE_GPP_D05 */
 157         PAD_NC(GPP_D05, NONE),
 158         /* GPP_D06 : [] ==> SPARE_GPP_D06 */
 159         PAD_NC(GPP_D06, NONE),
 160         /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL */
 161         PAD_NC(GPP_D07, NONE),
 162         /* GPP_D08 : [] ==> SPARE_GPP_D08 */
 163         PAD_NC(GPP_D08, NONE),
 164         /* GPP_D09 : [] ==> I2S_MCLK_R */
 165         PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
 166         /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */
 167         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
 168         /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */
 169         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
 170         /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */
 171         PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2),
 172         /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */
 173         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
 174         /* GPP_D14 : [] ==> I2S_HP_SCLK_R */
 175         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2),
 176         /* GPP_D15 : [] ==> I2S_HP_SFRM_R */
 177         PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2),
 178         /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */
 179         PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
 180         /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */
 181         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
 182         /* GPP_D18 : [] ==> LAN_PE_WAKE_ODL */
 183         PAD_CFG_GPI_SCI_LOW(GPP_D18, NONE, DEEP, EDGE_SINGLE),
 184         /* GPP_D19 : [] ==> SSD_CLKREQ_ODL */
 185         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 186         /* GPP_D20 : [] ==> LAN_CLKREQ_ODL */
 187         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 188         /* GPP_D21 : [] ==> WLAN_CLKREQ_ODL */
 189         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
 190         /* GPP_D22 : [] ==> NC */
 191         PAD_NC(GPP_D22, NONE),
 192         /* GPP_D23 : [] ==> NC */
 193         PAD_NC(GPP_D23, NONE),
 194
 195         /* GPP_E00 : [] ==> SAR_INT_L */
 196         PAD_NC(GPP_E00, NONE),
 197         /* GPP_E01 : [] ==> MEM_STRAP_2 */
 198         PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG),
 199         /* GPP_E02 : [] ==> MEM_STRAP_1 */
 200         PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG),
 201         /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
 202         PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
 203         /* GPP_E04 : [] ==> HPS_INT_L */
 204         PAD_NC(GPP_E04, NONE),
 205         /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */
 206         PAD_CFG_GPO(GPP_E05, 1, DEEP),
 207         /* GPP_E06 : [] ==> GPP_E06_STRAP */
 208         PAD_NC(GPP_E06, NONE),
 209         /* GPP_E07 : [] ==> WWAN_FCPO_L */
 210         PAD_NC(GPP_E07, NONE),
 211         /* GPP_E08 : [] ==> SAR2_INT_L */
 212         PAD_NC(GPP_E08, NONE),
 213         /* GPP_E09 : [] ==> USB_C_OC_ODL */
 214         PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG),
 215         /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */
 216         PAD_NC(GPP_E10, NONE),
 217         /* GPP_E11 : [] ==> MEM_STRAP_0 */
 218         PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 219         /* GPP_E12 : [] ==> MEM_STRAP_3 */
 220         PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 221         /* GPP_E13 : [] ==> MEM_CH_SEL */
 222         PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 223         /* GPP_E14 : [] ==> SOC_EDP_HPD_L */
 224         PAD_NC(GPP_E14, NONE),
 225         /* GPP_E15 : [] ==> NC */
 226         PAD_NC(GPP_E15, NONE),
 227         /* GPP_E16 : [] ==> GPP_E16 */
 228         PAD_NC(GPP_E16, NONE),
 229         /* GPP_E17 : [] ==> EN_HPS_PWR */
 230         PAD_NC(GPP_E17, NONE),
 231         /* GPP_E22 : [] ==> EN_WLAN_RAILS */
 232         PAD_CFG_GPO(GPP_E22, 1, DEEP),
 233
 234         /* GPP_F00 : [] ==> CNV_BRI_DT_R */
 235         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 236         /* GPP_F01 : [] ==> CNV_BRI_RSP */
 237         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, UP_20K, DEEP, NF1),
 238         /* GPP_F02 : [] ==> CNV_RGI_DT_R */
 239         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
 240         /* GPP_F03 : [] ==> CNV_RGI_RSP */
 241         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, UP_20K, DEEP, NF1),
 242         /* GPP_F04 : [] ==> CNV_RF_RST_L */
 243         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 244         /* GPP_F05 : [] ==> WLAN_CNVI_CLKREQ_ODL */
 245         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 246         /* GPP_F06 : [] ==> WWAN_WLAN_COEX3 */
 247         PAD_NC(GPP_F06, NONE),
 248         /* GPP_F07 : [] ==> UCAM_MCLK_R */
 249         PAD_NC(GPP_F07, NONE),
 250         /* GPP_F08 : [] ==> WLAN_PERST_L */
 251         PAD_CFG_GPO(GPP_F08, 1, DEEP),
 252         /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */
 253         PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT),
 254         /* GPP_F10 : [] ==> WWAN_PE_WAKE_ODL */
 255         PAD_NC(GPP_F10, NONE),
 256         /* GPP_F11 : [] ==> GSP1_SOC_CLK_R */
 257         PAD_NC(GPP_F11, NONE),
 258         /* GPP_F12 : [] ==> Net Name Correction: GSPI1_SOC_DO_FPMCU_DI_R */
 259         PAD_NC(GPP_F12, NONE),
 260         /* GPP_F13 : [] ==> Net Name Correction: GSPI1_SOC_DI_FPMCU_DO_LS */
 261         PAD_NC(GPP_F13, NONE),
 262         /* GPP_F14 : [] ==> GSPI_SOC_DO_TCHSCR_DI */
 263         PAD_NC(GPP_F14, NONE),
 264         /* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */
 265         PAD_NC(GPP_F15, NONE),
 266         /* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */
 267         PAD_NC(GPP_F16, NONE),
 268         /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
 269         PAD_NC(GPP_F17, NONE),
 270         /* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */
 271         PAD_NC(GPP_F18, NONE),
 272         /* GPP_F19 : [] ==> GPP_F19_STRAP */
 273         PAD_NC(GPP_F19, NONE),
 274         /* GPP_F20 : [] ==> GPP_F20_STRAP */
 275         PAD_NC(GPP_F20, NONE),
 276         /* GPP_F21 : [] ==> GPP_F21_STRAP */
 277         PAD_NC(GPP_F21, NONE),
 278         /* GPP_F22 : [] ==> NC */
 279         PAD_NC(GPP_F22, NONE),
 280         /* GPP_F23 : [] ==> NC */
 281         PAD_NC(GPP_F23, NONE),
 282
 283         /* GPP_H00 : [] ==> GPP_H00_STRAP */
 284         PAD_NC(GPP_H00, NONE),
 285         /* GPP_H01 : [] ==> GPP_H01_STRAP */
 286         PAD_NC(GPP_H01, NONE),
 287         /* GPP_H02 : [] ==> GPP_H02_STRAP */
 288         PAD_NC(GPP_H02, NONE),
 289         /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */
 290         PAD_NC(GPP_H04, NONE),
 291         /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */
 292         PAD_NC(GPP_H05, NONE),
 293         /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */
 294         PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG),
 295         /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */
 296         PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG),
 297         /* GPP_H08 : [] ==> UART_SOC_RX_DEBUG_TX */
 298         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 299         /* GPP_H09 : [] ==> UART_SOC_TX_DEBUG_RX */
 300         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 301         /* GPP_H10 : [] ==> SOC_WP_OD */
 302         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 303         /* GPP_H11 : [] ==> USB_A1_RT_RST_ODL */
 304         PAD_NC(GPP_H11, NONE),
 305         /* GPP_H13 : [] ==> CPU_C10_GATE_L */
 306         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 307         /* GPP_H14 : [] ==> SLP_S0_GATE_R */
 308         PAD_CFG_GPO(GPP_H14, 1, PLTRST),
 309         /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */
 310         PAD_CFG_GPO(GPP_H15, 0, PLTRST),
 311         /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK */
 312         PAD_NC(GPP_H16, NONE),
 313         /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */
 314         PAD_NC(GPP_H17, NONE),
 315         /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */
 316         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 317         /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */
 318         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 319         /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */
 320         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 321         /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */
 322         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 323
 324         /* GPP_S00 : [] ==> SDW_HP_CLK */
 325         PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 326         /* GPP_S01 : [] ==> SDW_HP_DATA */
 327         PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
 328         /* GPP_S02 : [] ==> DMIC_SOC_CLK0_DB_RC */
 329         PAD_NC(GPP_S02, NONE),
 330         /* GPP_S03 : [] ==> DMIC_SOC_DATA0_DB_R */
 331         PAD_NC(GPP_S03, NONE),
 332         /* GPP_S04 : [] ==> SDW_SPKR_CLK */
 333         PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1),
 334         /* GPP_S05 : [] ==> SDW_SPKR_DATA */
 335         PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1),
 336         /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */
 337         PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
 338         /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */
 339         PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
 340
 341         /* GPP_V00 : [] ==> BATLOW_L */
 342         PAD_NC(GPP_V00, NONE),
 343         /* GPP_V01 : [] ==> ACPRESENT */
 344         PAD_NC(GPP_V01, NONE),
 345         /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */
 346         PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 347         /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */
 348         PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 349         /* GPP_V04 : [] ==> SLP_S3_L */
 350         PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 351         /* GPP_V05 : [] ==> SLP_S4_L */
 352         PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 353         /* GPP_V06 : [] ==> SLP_A_L */
 354         PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
 355         /* GPP_V08 : [] ==> SOC_SUSCLK */
 356         PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 357         /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */
 358         PAD_NC(GPP_V09, NONE),
 359         /* GPP_V10 : [] ==> SLP_S5_L */
 360         PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
 361         /* GPP_V11 : [] ==> SOC_GPP_V11 */
 362         PAD_NC(GPP_V11, NONE),
 363         /* GPP_V12 : [] ==> SOC_SLP_LAN_L */
 364         PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 365         /* GPP_V14 : [] ==> SOC_WAKE_L */
 366         PAD_NC(GPP_V14, NONE),
 367         /* GPP_V22 : [] ==> WCAM_RST_L */
 368         PAD_NC(GPP_V22, NONE),
 369         /* GPP_V23 : [] ==> UCAM_RST_L */
 370         PAD_NC(GPP_V23, NONE),
 371 };
 372
 373 /* Early pad configuration in bootblock */
 374 static const struct pad_config early_gpio_table[] = {
 375         /* GPP_A20 : [] ==> SSD_PERST_L */
 376         PAD_CFG_GPO(GPP_A20, 0, DEEP),
 377
 378         /* GPP_B18 : [] ==> I2C4_SDA */
 379         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
 380         /* GPP_B19 : [] ==> I2C4_SCL */
 381         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
 382         /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
 383         PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
 384
 385         /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
 386         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 387         /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
 388         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 389
 390         /* GPP_D03 : [] ==> EN_SD_RAILS */
 391         PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG),
 392
 393         /* GPP_E13 :  [] ==> MEM_CH_SEL */
 394         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 395
 396         /* GPP_C13 : [] ==> LAN_PERST_L */
 397         PAD_CFG_GPO(GPP_C13, 0, DEEP),
 398
 399         /* GPP_H10 : [] ==> SOC_WP_OD */
 400         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 401
 402         /* GPP_D02 : [] ==> SD_PERST_L */
 403         PAD_CFG_GPO(GPP_D02, 0, DEEP),
 404
 405         /* GPP_A19 : [] ==> EN_PP3300_SSD */
 406         PAD_CFG_GPO(GPP_A19, 1, DEEP),
 407 };
 408
 409 static const struct pad_config romstage_gpio_table[] = {
 410         /* GPP_C13 : [] ==> LAN_PERST_L */
 411         PAD_CFG_GPO(GPP_C13, 0, DEEP),
 412         /* GPP_D02 : [] ==> SD_PERST_L */
 413         PAD_CFG_GPO(GPP_D02, 0, DEEP),
 414         /* GPP_A20 : [] ==> SSD_PERST_L */
 415         PAD_CFG_GPO(GPP_A20, 1, DEEP),
 416 };
 417
 418 const struct pad_config *variant_gpio_table(size_t *num)
 419 {
 420         *num = ARRAY_SIZE(gpio_table);
 421         return gpio_table;
 422 }
 423
 424 const struct pad_config *variant_early_gpio_table(size_t *num)
 425 {
 426         *num = ARRAY_SIZE(early_gpio_table);
 427         return early_gpio_table;
 428 }
 429
 430 /* Create the stub for romstage gpio, typically use for power sequence */
 431 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 432 {
 433         *num = ARRAY_SIZE(romstage_gpio_table);
 434         return romstage_gpio_table;
 435 }
 436
 437 static const struct cros_gpio cros_gpios[] = {
 438         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 439         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 440 };
 441
 442 DECLARE_CROS_GPIOS(cros_gpios);