src/mainboard/google/rex/variants/screebo/memory.c

   1 /* SPDX-License-Identifier: GPL-3.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6
   7 static const struct mb_cfg baseboard_memcfg = {
   8         .type = MEM_TYPE_LP5X,
   9
  10         .rcomp = {
  11                 /* Baseboard uses only 100ohm Rcomp resistors */
  12                 .resistor = 100,
  13         },
  14
  15         /* DQ byte map */
  16         .lpx_dq_map = {
  17                 .ddr0 = {
  18                         .dq0 = {  9, 13, 12,  14, 8, 10, 11, 15 },
  19                         .dq1 = {  6,  5,  7,   4, 3,  2,  0,  1 },
  20                 },
  21                 .ddr1 = {
  22                         .dq0 = {  2,  0,  1,  3,  4,  5,  6,  7 },
  23                         .dq1 = { 14,  8, 12, 15, 11, 10,  9, 13 },
  24                 },
  25                 .ddr2 = {
  26                         .dq0 = {  9, 11, 10,  8, 15, 13, 14, 12 },
  27                         .dq1 = {  0,  6,  2,  3,  1,  4,  5,  7 },
  28                 },
  29                 .ddr3 = {
  30                         .dq0 = {  7,  2,  0,  3,  4,  1,  5,  6 },
  31                         .dq1 = {  8, 14, 12, 13, 11, 15,  9, 10 },
  32                 },
  33                 .ddr4 = {
  34                         .dq0 = { 14,  9, 12, 15, 11, 10,  8, 13 },
  35                         .dq1 = {  5,  7,  4,  6,  2,  1,  0,  3 },
  36                 },
  37                 .ddr5 = {
  38                         .dq0 = {  1,  5,  3,  6,  2,  7,  0,  4 },
  39                         .dq1 = { 10,  8, 11,  9, 12, 15, 14, 13 },
  40                 },
  41                 .ddr6 = {
  42                         .dq0 = { 10,  8,  9, 11, 13, 14, 15, 12 },
  43                         .dq1 = {  3,  7,  2,  0,  1,  4,  6,  5 },
  44                 },
  45                 .ddr7 = {
  46                         .dq0 = {  1,  2,  3,  0,  5,  7,  4,  6 },
  47                         .dq1 = { 14,  8, 12, 13, 15, 11, 10,  9 },
  48                 },
  49         },
  50
  51         /* DQS CPU<>DRAM map */
  52         .lpx_dqs_map = {
  53                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  54                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  55                 .ddr2 = { .dqs0 = 1, .dqs1 = 0 },
  56                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  57                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  58                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  59                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  60                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  61         },
  62
  63         .lp5x_config = {
  64                 .ccc_config = 0xaa,
  65         },
  66
  67         .ect = 1, /* Early Command Training */
  68 };
  69
  70 const struct mb_cfg *variant_memory_params(void)
  71 {
  72         return &baseboard_memcfg;
  73 }
  74
  75 int variant_memory_sku(void)
  76 {
  77         gpio_t spd_gpios[] = {
  78                 GPIO_MEM_CONFIG_0,
  79                 GPIO_MEM_CONFIG_1,
  80                 GPIO_MEM_CONFIG_2,
  81                 GPIO_MEM_CONFIG_3,
  82         };
  83
  84         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  85 }
  86
  87 bool variant_is_half_populated(void)
  88 {
  89         return gpio_get(GPIO_MEM_CH_SEL);
  90 }
  91
  92 void variant_get_spd_info(struct mem_spd *spd_info)
  93 {
  94         spd_info->topo = MEM_TOPO_MEMORY_DOWN;
  95         spd_info->cbfs_index = variant_memory_sku();
  96 }