mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / lenovo / t60 / variants / z61t / overridetree.cb
blob00f3f198e370fb27b76687e57f432e8f6ce31ebc
1 ## SPDX-License-Identifier: GPL-2.0-only
3 chip northbridge/intel/i945
4 device domain 0 on
5 device pci 00.0 on # Host bridge
6 subsystemid 0x17aa 0x2017
7 end
8 device pci 01.0 on # PEG
9 device pci 00.0 on end # VGA
10 end
11 chip southbridge/intel/i82801gx
12 device pci 1c.0 on # PCI Express Port 1
13 subsystemid 0x17aa 0x2011
14 end
15 device pci 1c.1 on # PCI Express Port 2
16 subsystemid 0x17aa 0x2011
17 end
18 device pci 1c.2 on # PCI Express Port 3
19 subsystemid 0x17aa 0x2011
20 end
21 device pci 1c.3 on # PCI Express Port 4
22 subsystemid 0x17aa 0x2011
23 end
24 device pci 1e.0 on # PCI Bridge
25 chip southbridge/ti/pci1x2x
26 device pci 00.0 on
27 subsystemid 0x17aa 0x2013
28 end
29 end
30 end
31 device pci 1f.0 on # PCI-LPC bridge
32 chip superio/nsc/pc87384
33 device pnp 2e.2 off # Serial Port / IR
34 irq 0x70 = 3
35 end
36 end
37 end
38 device pci 1f.3 on # SMBUS
39 chip drivers/i2c/ck505
40 register "mask" = "{ 0xff, 0xff, 0xff,
41 0xff, 0xff, 0xff, 0xff, 0xff }"
42 # vendor clockgen setup
43 register "regs" = "{ 0x6d, 0xff, 0xff,
44 0x20, 0x41, 0x7f, 0x18, 0x00 }"
45 device i2c 69 on end
46 end
47 end
48 end
49 end
50 end