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mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / libretrend / lt1000 / devicetree.cb
blob4f7d7eb6313c5c61f13b6db171b74faf85cf294f
1 chip soc/intel/skylake
2
3 # Enable deep Sx states
4 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "0"
6 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
8 register "deep_sx_config" = "DSX_EN_WAKE_PIN"
9
10 register "eist_enable" = "true"
11
12 # Set the Thermal Control Circuit (TCC) activation value to 95C
13 # even though FSP integration guide says to set it to 100C for SKL-U
14 # (offset at 0), because when the TCC activates at 100C, the CPU
15 # will have already shut itself down from overheating protection.
16 register "tcc_offset" = "5" # TCC of 95C
17
18 # GPE configuration
19 # Note that GPE events called out in ASL code rely on this
20 # route. i.e. If this route changes then the affected GPE
21 # offset bits also need to be changed.
22 register "gpe0_dw0" = "GPP_C"
23 register "gpe0_dw1" = "GPP_D"
24 register "gpe0_dw2" = "GPP_E"
25
26 # Disable DPTF
27 register "dptf_enable" = "0"
28
29 # FSP Configuration
30 register "DspEnable" = "1"
31 register "IoBufferOwnership" = "0"
32 register "SkipExtGfxScan" = "1"
33 register "SaGv" = "SaGv_Enabled"
34 register "PmConfigSlpS3MinAssert" = "2" # 50ms
35 register "PmConfigSlpS4MinAssert" = "1" # 1s
36 register "PmConfigSlpSusMinAssert" = "3" # 500ms
37 register "PmConfigSlpAMinAssert" = "3" # 2s
38
39 # VR Settings Configuration for 4 Domains
40 #+----------------+-------+-------+-------------+-------+
41 #| Domain/Setting | SA | IA | GT-Unsliced | GT |
42 #+----------------+-------+-------+-------------+-------+
43 #| Psi1Threshold | 20A | 20A | 20A | 20A |
44 #| Psi2Threshold | 4A | 5A | 5A | 5A |
45 #| Psi3Threshold | 1A | 1A | 1A | 1A |
46 #| Psi3Enable | 1 | 1 | 1 | 1 |
47 #| Psi4Enable | 1 | 1 | 1 | 1 |
48 #| ImonSlope | 0 | 0 | 0 | 0 |
49 #| ImonOffset | 0 | 0 | 0 | 0 |
50 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
51 #+----------------+-------+-------+-------------+-------+
52 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
53 .vr_config_enable = 1,
54 .psi1threshold = VR_CFG_AMP(20),
55 .psi2threshold = VR_CFG_AMP(4),
56 .psi3threshold = VR_CFG_AMP(1),
57 .psi3enable = 1,
58 .psi4enable = 1,
59 .imon_slope = 0x0,
60 .imon_offset = 0x0,
61 .voltage_limit = 1520,
62 }"
63
64 register "domain_vr_config[VR_IA_CORE]" = "{
65 .vr_config_enable = 1,
66 .psi1threshold = VR_CFG_AMP(20),
67 .psi2threshold = VR_CFG_AMP(5),
68 .psi3threshold = VR_CFG_AMP(1),
69 .psi3enable = 1,
70 .psi4enable = 1,
71 .imon_slope = 0x0,
72 .imon_offset = 0x0,
73 .voltage_limit = 1520,
74 }"
75
76 register "domain_vr_config[VR_GT_UNSLICED]" = "{
77 .vr_config_enable = 1,
78 .psi1threshold = VR_CFG_AMP(20),
79 .psi2threshold = VR_CFG_AMP(5),
80 .psi3threshold = VR_CFG_AMP(1),
81 .psi3enable = 1,
82 .psi4enable = 1,
83 .imon_slope = 0x0,
84 .imon_offset = 0x0,
85 .voltage_limit = 1520,
86 }"
87
88 register "domain_vr_config[VR_GT_SLICED]" = "{
89 .vr_config_enable = 1,
90 .psi1threshold = VR_CFG_AMP(20),
91 .psi2threshold = VR_CFG_AMP(5),
92 .psi3threshold = VR_CFG_AMP(1),
93 .psi3enable = 1,
94 .psi4enable = 1,
95 .imon_slope = 0x0,
96 .imon_offset = 0x0,
97 .voltage_limit = 1520,
98 }"
99
100 register "PcieRpClkSrcNumber[0]" = "0"
101
102 # PL2 override 25W
103 register "power_limits_config" = "{
104 .tdp_pl2_override = 25,
105 }"
106
107 # Send an extra VR mailbox command for the PS4 exit issue
108 register "SendVrMbxCmd" = "2"
109
110 device domain 0 on
111 device ref igpu on end
112 device ref sa_thermal on end
113 device ref south_xhci on
114 register "usb2_ports" = "{
115 [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
116 [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
117 [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
118 [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
119 [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
120 [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
121 [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
122 [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
123 }"
124
125 register "usb3_ports" = "{
126 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
127 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
128 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
129 [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
130 }"
131 end
132 device ref south_xdci on end
133 device ref thermal on end
134 device ref heci1 on end
135 device ref sata on
136 register "SataPortsEnable" = "{
137 [0] = 1,
138 [1] = 1,
139 [2] = 1,
140 }"
141 register "SataSpeedLimit" = "2"
142 end
143 device ref pcie_rp3 on
144 register "PcieRpEnable[2]" = "1"
145 end
146 device ref pcie_rp4 on
147 register "PcieRpEnable[3]" = "1"
148 register "PcieRpClkSrcNumber[3]" = "1"
149 end
150 device ref pcie_rp5 on
151 register "PcieRpEnable[4]" = "1"
152 register "PcieRpClkSrcNumber[4]" = "2"
153 smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
154 "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X"
155 end
156 device ref pcie_rp6 on end
157 device ref pcie_rp9 on
158 register "PcieRpEnable[8]" = "1"
159 register "PcieRpClkSrcNumber[8]" = "3"
160 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
161 "SSD_M.2 2242/2280" "SlotDataBusWidth4X"
162 end
163 device ref pcie_rp10 on
164 register "PcieRpEnable[9]" = "1"
165 register "PcieRpClkSrcNumber[9]" = "3"
166 end
167 device ref pcie_rp11 on
168 register "PcieRpEnable[10]" = "1"
169 register "PcieRpClkSrcNumber[10]" = "3"
170 end
171 device ref pcie_rp12 on
172 register "PcieRpEnable[11]" = "1"
173 register "PcieRpClkSrcNumber[11]" = "3"
174 end
175 device ref lpc_espi on
176 register "serirq_mode" = "SERIRQ_CONTINUOUS"
177
178 register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
179 register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
180 register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
181 chip drivers/pc80/tpm
182 device pnp 0c31.0 on end
183 end
184 chip superio/ite/it8786e
185 register "TMPIN1.mode" = "THERMAL_PECI"
186 register "TMPIN1.offset" = "100"
187 register "TMPIN1.min" = "128"
188 register "TMPIN2.mode" = "THERMAL_RESISTOR"
189 register "TMPIN2.min" = "128"
190 register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
191 register "ec.vin_mask" = "VIN_ALL"
192 # FAN1 is CPU fan (on board)
193 register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
194 register "FAN1.smart.tmpin" = " 1"
195 register "FAN1.smart.tmp_off" = "35"
196 register "FAN1.smart.tmp_start" = "60"
197 register "FAN1.smart.tmp_full" = "85"
198 register "FAN1.smart.tmp_delta" = " 2"
199 register "FAN1.smart.pwm_start" = "20"
200 register "FAN1.smart.slope" = "24"
201 # FAN2 is system fan (4 pin connector populated)
202 #register "FAN2.mode" = "FAN_MODE_OFF"
203 # FAN3 PWM is used for LVDS backlight control
204 #register "FAN3.mode" = "FAN_MODE_OFF"
205
206 device pnp 2e.1 on # COM 1
207 io 0x60 = 0x3f8
208 irq 0x70 = 4
209 end
210 device pnp 2e.2 on # COM 2
211 io 0x60 = 0x2f8
212 irq 0x70 = 3
213 end
214 device pnp 2e.3 on # Printer Port
215 io 0x60 = 0x378
216 io 0x62 = 0x778
217 irq 0x70 = 5
218 drq 0x74 = 3
219 end
220 device pnp 2e.4 on # Environment Controller
221 io 0x60 = 0xa40
222 io 0x62 = 0xa30
223 irq 0x70 = 9
224 end
225 device pnp 2e.5 on # Keyboard
226 io 0x60 = 0x60
227 io 0x62 = 0x64
228 irq 0x70 = 1
229 end
230 device pnp 2e.6 on # Mouse
231 irq 0x70 = 12
232 end
233 device pnp 2e.7 off # GPIO
234 end
235 device pnp 2e.8 on # COM 3
236 io 0x60 = 0x3e8
237 irq 0x70 = 3
238 end
239 device pnp 2e.9 on # COM 4
240 io 0x60 = 0x2e8
241 irq 0x70 = 4
242 end
243 device pnp 2e.a off end # CIR
244 device pnp 2e.b on # COM 5
245 io 0x60 = 0x2f0
246 irq 0x70 = 3
247 end
248 device pnp 2e.c on # COM 6
249 io 0x60 = 0x2e0
250 irq 0x70 = 4
251 end
252 end
253 end
254 device ref hda on end
255 device ref smbus on end
256 device ref fast_spi on end
257 end
258 end
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