mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / msi / ms7707 / early_init.c
blob24ba8ebfa546211b81dc2f255b159c8d1c3ec69a
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci_ops.h>
4 #include <southbridge/intel/common/pmbase.h>
5 #include <southbridge/intel/bd82x6x/pch.h>
7 void mainboard_pch_lpc_setup(void)
9 u16 reg16;
10 reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
11 reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
12 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
15 const struct southbridge_usb_port mainboard_usb_ports[] = {
16 {1, 0, 0},
17 {1, 0, 0},
18 {1, 0, 1},
19 {1, 0, 1},
20 {1, 0, 2},
21 {1, 0, 2},
22 {1, 0, 3},
23 {1, 0, 3},
24 {1, 0, 4},
25 {1, 0, 4},
26 {1, 0, 6},
27 {1, 0, 5},
28 {1, 0, 5},
29 {1, 0, 6},