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mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / msi / ms7e06 / devicetree.cb
blobeb179885c17c795904b2552c74dd24d6480b7b99
1 chip soc/intel/alderlake
2 # FSP configuration
3
4 register "eist_enable" = "true"
5
6 # Sagv Configuration
7 register "sagv" = "SaGv_Enabled"
8 register "RMT" = "0"
9 register "enable_c6dram" = "1"
10
11 register "pmc_gpe0_dw0" = "GPP_J"
12 register "pmc_gpe0_dw1" = "GPP_VPGIO"
13 register "pmc_gpe0_dw2" = "GPD"
14
15 register "hybrid_storage_mode" = "true"
16 register "dmi_power_optimize_disable" = "true"
17
18 # FIVR configuration
19 register "fivr_rfi_frequency" = "1394"
20 register "fivr_spread_spectrum" = "FIVR_SS_1_5"
21 register "ext_fivr_settings" = "{
22 .configure_ext_fivr = 1,
23 }"
24
25 device domain 0 on
26 subsystemid 0x1462 0x7e06 inherit
27 device ref pcie5_0 on
28 register "cpu_pcie_rp[CPU_RP(2)]" = "{
29 .clk_src = 0,
30 .clk_req = 0,
31 .flags = PCIE_RP_LTR | PCIE_RP_AER,
32 }"
33 smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
34 "PCI_E1" "SlotDataBusWidth16X"
35 end
36 device ref igpu on
37 # HDMI on port B
38 register "ddi_portB_config" = "1"
39 register "ddi_ports_config" = "{
40 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
41 [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
42 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
43 [DDI_PORT_2] = DDI_ENABLE_HPD,
44 [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
45 [DDI_PORT_4] = DDI_ENABLE_HPD,
46 }"
47 end
48 device ref pcie4_0 on
49 register "cpu_pcie_rp[CPU_RP(1)]" = "{
50 .clk_src = 9,
51 .clk_req = 9,
52 .flags = PCIE_RP_LTR | PCIE_RP_AER,
53 }"
54 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
55 "M2_1" "SlotDataBusWidth4X"
56 end
57 device ref xhci on
58 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1
59 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT
60 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1
61 register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5
62 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0
63 register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
64 register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4
65 register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4
66 register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3
67 register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3
68 register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
69 register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
70 register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers
71 register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT
72 register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
73 register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
74
75 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
76 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
77 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
78 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
79 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
80 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
81 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
82 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
83 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
84 register "usb3_ports[9]" = "USB3_PORT_EMPTY"
85 end
86 device ref cnvi_wifi on
87 # Enable CNVi BT
88 register "cnvi_bt_core" = "true"
89 register "cnvi_bt_audio_offload" = "false"
90 chip drivers/wifi/generic
91 register "wake" = "GPE0_PME_B0"
92 register "enable_cnvi_ddr_rfim" = "true"
93 device generic 0 on end
94 end
95 end
96 device ref heci1 on end
97 device ref sata on
98 register "sata_salp_support" = "1"
99
100 register "sata_ports_enable" = "{
101 [0] = 1,
102 [1] = 1,
103 [2] = 1,
104 [3] = 1,
105 [4] = 1,
106 [5] = 1,
107 [6] = 1,
108 [7] = 1,
109 }"
110
111 register "sata_ports_dev_slp" = "{
112 [0] = 0,
113 [1] = 0,
114 [2] = 0,
115 [3] = 0,
116 [4] = 0,
117 [5] = 0,
118 [6] = 1,
119 [7] = 1,
120 }"
121 end
122 device ref pcie_rp1 on
123 register "pch_pcie_rp[PCH_RP(1)]" = "{
124 .clk_src = 10,
125 .clk_req = 10,
126 .flags = PCIE_RP_LTR | PCIE_RP_AER,
127 }"
128 smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
129 "PCI_E2" "SlotDataBusWidth1X"
130 end
131 device ref pcie_rp2 on
132 register "pch_pcie_rp[PCH_RP(2)]" = "{
133 .clk_src = 17,
134 .clk_req = 17,
135 .flags = PCIE_RP_LTR | PCIE_RP_AER,
136 }"
137 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
138 "PCI_E4" "SlotDataBusWidth1X"
139 end
140 device ref pcie_rp3 on
141 # i225 Ethernet, Clock PM unsupported, onboard device
142 register "pch_pcie_rp[PCH_RP(3)]" = "{
143 .clk_src = 12,
144 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
145 }"
146 end
147
148 device ref pcie_rp5 on
149 register "pch_pcie_rp[PCH_RP(5)]" = "{
150 .clk_src = 15,
151 .clk_req = 15,
152 .flags = PCIE_RP_LTR | PCIE_RP_AER,
153 }"
154 smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong"
155 "PCI_E3" "SlotDataBusWidth4X"
156 end
157
158 device ref pcie_rp9 on
159 register "pch_pcie_rp[PCH_RP(9)]" = "{
160 .clk_src = 13,
161 .clk_req = 13,
162 .flags = PCIE_RP_LTR | PCIE_RP_AER,
163 }"
164 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
165 "M2_3" "SlotDataBusWidth4X"
166 end
167
168 # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
169 # There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
170 # 9-12, 21-24 to M2_3 and M2_4 slots
171 device ref pcie_rp13 off end
172 device ref pcie_rp14 off end
173 device ref pcie_rp15 off end
174 device ref pcie_rp16 off end
175 device ref pcie_rp17 off end
176 device ref pcie_rp18 off end
177 device ref pcie_rp19 off end
178 device ref pcie_rp20 off end
179
180 device ref pcie_rp21 on
181 register "pch_pcie_rp[PCH_RP(21)]" = "{
182 .clk_src = 14,
183 .clk_req = 14,
184 .flags = PCIE_RP_LTR | PCIE_RP_AER,
185 }"
186 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
187 "M2_4" "SlotDataBusWidth4X"
188 end
189
190 device ref pcie_rp25 on
191 register "pch_pcie_rp[PCH_RP(25)]" = "{
192 .clk_src = 8,
193 .clk_req = 8,
194 .flags = PCIE_RP_LTR | PCIE_RP_AER,
195 }"
196 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
197 "M2_2" "SlotDataBusWidth4X"
198 end
199 device ref pch_espi on
200 register "gen1_dec" = "0x00fc0201"
201 register "gen2_dec" = "0x003c0a01"
202 register "gen3_dec" = "0x000c03f1"
203 register "gen4_dec" = "0x000c0081"
204
205 chip superio/nuvoton/nct6687d
206 device pnp 4e.1 off end # Parallel port
207 device pnp 4e.2 on # COM1
208 io 0x60 = 0x3f8
209 irq 0x70 = 4
210 end
211 device pnp 4e.3 off end # COM2, IR
212 device pnp 4e.5 on # Keyboard
213 io 0x60 = 0x60
214 io 0x62 = 0x64
215 irq 0x70 = 1
216 irq 0x72 = 12
217 end
218 device pnp 4e.6 off end # CIR
219 device pnp 4e.7 off end # GPIO0-7
220 device pnp 4e.8 off end # P80 UART
221 device pnp 4e.9 off end # GPIO8-9, GPIO1-8 AF
222 device pnp 4e.a on # ACPI
223 # Vendor firmware did not assign I/O and IRQ
224 end
225 device pnp 4e.b on # EC
226 io 0x60 = 0xa20
227 # Vendor firmware did not assign IRQ
228 end
229 device pnp 4e.c off end # RTC
230 device pnp 4e.d off end # Deep Sleep
231 device pnp 4e.e off end # TACH/PWM assignment
232 device pnp 4e.f off end # Function register
233 end
234 chip drivers/pc80/tpm
235 device pnp 0.0 on end # TPM
236 end
237 end
238 device ref hda on
239 subsystemid 0x1462 0x9e06
240 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
241 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
242 register "pch_hda_idisp_codec_enable" = "true"
243 end
244 device ref smbus on end
245
246 chip drivers/crb
247 device mmio 0xfed40000 on end
248 end
249 end
250 end
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