src/mainboard/pcengines/apu2/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <northbridge/amd/agesa/state_machine.h>
   5
   6 #include "gpio_ftns.h"
   7
   8 static const PCIe_PORT_DESCRIPTOR PortList[] = {
   9         {
  10                 0,
  11                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
  12                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
  13                                 HotplugDisabled,
  14                                 PcieGenMaxSupported,
  15                                 PcieGenMaxSupported,
  16                                 AspmL0sL1,
  17                                 0x01,
  18                                 0)
  19         },
  20         /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
  21         {
  22                 0,
  23                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
  24                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
  25                                 HotplugDisabled,
  26                                 PcieGenMaxSupported,
  27                                 PcieGenMaxSupported,
  28                                 AspmL0sL1,
  29                                 0x02,
  30                                 0)
  31         },
  32         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  33         {
  34                 0,
  35                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
  36                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
  37                                 HotplugDisabled,
  38                                 PcieGenMaxSupported,
  39                                 PcieGenMaxSupported,
  40                                 AspmL0sL1,
  41                                 0x03,
  42                                 0)
  43         },
  44         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  45         {
  46                 0,
  47                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
  48                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
  49                                 HotplugDisabled,
  50                                 PcieGenMaxSupported,
  51                                 PcieGenMaxSupported,
  52                                 AspmL0sL1,
  53                                 0x04,
  54                                 0)
  55         },
  56         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
  57         {
  58                 DESCRIPTOR_TERMINATE_LIST,
  59                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  60                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
  61                                 HotplugDisabled,
  62                                 PcieGenMaxSupported,
  63                                 PcieGenMaxSupported,
  64                                 AspmL0sL1,
  65                                 0x05,
  66                                 0)
  67         }
  68 };
  69
  70 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  71         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  72         .SocketId     = 0,
  73         .PciePortList = PortList,
  74         .DdiLinkList  = NULL,
  75 };
  76
  77 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  78 {
  79         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  80         InitEarly->PlatformConfig.CStateMode = CStateModeC6;
  81         InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
  82 }
  83
  84 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
  85 {
  86         /*
  87          * Bank interleaving does not work on this platform.
  88          * Disable it so AGESA will return success.
  89          */
  90         Post->MemConfig.EnableBankIntlv = FALSE;
  91         /* 4GB variants have ECC */
  92         if (get_spd_offset())
  93                 Post->MemConfig.EnableEccFeature = TRUE;
  94         else
  95                 Post->MemConfig.EnableEccFeature = FALSE;
  96 }