mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / protectli / vault_ehl / devicetree.cb
blob10782b265d14c3f0ba847da95dcb734a88f9bf23
1 chip soc/intel/elkhartlake
3 #register "enable_vtd" = "1"
5 register "power_limits_config" = "{
6 .tdp_pl1_override = 10,
7 .tdp_pl2_override = 15,
8 }"
10 register "SaGv" = "SaGv_Enabled"
11 register "eist_enable" = "true"
13 # Enable lpss s0ix
14 register "s0ix_enable" = "true"
16 # GPE configuration
17 # Note that GPE events called out in ASL code rely on this
18 # route, i.e., if this route changes then the affected GPE
19 # offset bits also need to be changed. This sets the PMC register
20 # GPE_CFG fields.
21 #register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32"
22 #register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0"
23 #register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0"
25 register "tcc_offset" = "5" # TCC of 95C
27 # USB 2.0 ports
28 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1
29 register "usb2_ports[1]" = "USB2_PORT_EMPTY"
30 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1
31 register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WLAN
32 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WWAN
33 register "usb2_ports[5]" = "USB2_PORT_EMPTY"
34 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Upper
35 register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-C
36 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Lower
37 register "usb2_ports[9]" = "USB2_PORT_EMPTY"
39 # USB 3.x ports
40 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Upper
41 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Lower
42 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Muxed
43 register "usb3_ports[3]" = "USB3_PORT_EMPTY"
45 # PCIe root ports related UPDs
46 register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
47 register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
48 register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
49 register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
50 register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
51 register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
53 register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
54 register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
55 register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
56 register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
57 register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
58 register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
60 # Storage (SATA/SDCARD/EMMC) related UPDs
61 register "SataSalpSupport" = "1"
62 register "SataPortsEnable[0]" = "1" # Header
63 register "SataPortsEnable[1]" = "1" # M.2 2280
64 register "SataPortsDevSlp[0]" = "0"
65 register "SataPortsDevSlp[1]" = "1"
67 register "PchHdaAudioLinkHdaEnable" = "1"
68 register "PchHdaSdiEnable[0]" = "1"
69 register "ScsEmmcHs400Enabled" = "1"
70 register "SkipCpuReplacementCheck" = "1"
72 # Enable DDI ports A/B/C
73 register "DdiPortAConfig" = "1"
74 register "DdiPortBConfig" = "1"
75 register "DdiPortCConfig" = "1"
77 # Enable HPD for DDI ports A/B
78 register "DdiPortAHpd" = "1"
79 register "DdiPortBHpd" = "1"
81 # Enable DDC for DDI ports A/B
82 register "DdiPortADdc" = "1"
83 register "DdiPortBDdc" = "1"
85 device cpu_cluster 0 on end
86 device domain 0 on
87 device pci 00.0 on end # Host Bridge
88 device pci 02.0 on end # Integrated Graphics Device
89 device pci 04.0 off end # SA Thermal device
90 device pci 08.0 off end # GNA
91 device pci 09.0 off end # CPU Intel Trace Hub
93 device pci 10.0 on end # I2C6
94 device pci 10.1 on end # I2C7
95 device pci 10.5 on end # Integrated Error Handler
97 device pci 11.0 off end # Intel PSE UART0
98 device pci 11.1 off end # Intel PSE UART1
99 device pci 11.2 off end # Intel PSE UART2
100 device pci 11.3 off end # Intel PSE UART3
101 device pci 11.4 off end # Intel PSE UART4
102 device pci 11.5 off end # Intel PSE UART5
103 device pci 11.6 off end # Intel PSE IS20
104 device pci 11.7 off end # Intel PSE IS21
106 device pci 12.0 on end # GSPI2
107 device pci 12.3 on end # Management Engine UMA Access
108 device pci 12.4 on end # Management Engine PTT DMA Controller
109 device pci 12.5 off end # UFS0
110 device pci 12.7 off end # UFS1
112 device pci 13.0 off end # Intel PSE GSPI0
113 device pci 13.1 off end # Intel PSE GSPI1
114 device pci 13.2 off end # Intel PSE GSPI2
115 device pci 13.3 off end # Intel PSE GSPI3
116 device pci 13.4 off end # Intel PSE GPIO0
117 device pci 13.5 off end # Intel PSE GPIO1
119 device pci 14.0 on end # USB3.1 xHCI
120 device pci 14.1 off end # USB3.1 xDCI (OTG)
121 device pci 14.2 on end # Shared RAM
123 device pci 15.0 off end # I2C0
124 device pci 15.1 off end # I2C1
125 device pci 15.2 off end # I2C2
126 device pci 15.3 off end # I2C3
128 device pci 16.0 on end # Management Engine Interface 1
129 device pci 16.1 off end # Management Engine Interface 2
130 device pci 16.4 off end # Management Engine Interface 3
131 device pci 16.5 off end # Management Engine Interface 4
133 device pci 17.0 on end # SATA
135 device pci 18.0 off end # Intel PSE I2C7
136 device pci 18.1 off end # Intel PSE CAN0
137 device pci 18.2 off end # Intel PSE CAN1
138 device pci 18.3 off end # Intel PSE QEP0
139 device pci 18.4 off end # Intel PSE QEP1
140 device pci 18.5 off end # Intel PSE QEP2
141 device pci 18.6 off end # Intel PSE QEP3
143 device pci 19.0 on end # I2C4
144 device pci 19.1 off end # I2C5
145 device pci 19.2 on end # UART2
147 device pci 1a.0 on end # eMMC
148 device pci 1a.1 off end # SD
149 device pci 1a.3 off end # Intel Safety Island
151 device pci 1b.0 off end # Intel PSE I2C0
152 device pci 1b.1 off end # Intel PSE I2C1
153 device pci 1b.2 off end # Intel PSE I2C2
154 device pci 1b.3 off end # Intel PSE I2C3
155 device pci 1b.4 off end # Intel PSE I2C4
156 device pci 1b.5 off end # Intel PSE I2C5
157 device pci 1b.6 off end # Intel PSE I2C6
159 device pci 1c.0 on end # RP0 (pcie0 single VC)
160 device pci 1c.1 on end # RP1 (pcie0 single VC)
161 device pci 1c.2 on end # RP2 (pcie0 single VC)
162 device pci 1c.3 off end # RP3 (pcie0 single VC)
163 device pci 1c.4 on end # RP4 (pcie1 multi VC)
164 device pci 1c.5 off end # RP5 (pcie2 multi VC)
165 device pci 1c.6 on end # RP6 (pcie3 multi VC)
167 device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
168 device pci 1d.1 off end # Intel PSE Time-Sensitive Networking GbE 0
169 device pci 1d.2 off end # Intel PSE Time-Sensitive Networking GbE 1
170 device pci 1d.3 off end # Intel PSE DMA0
171 device pci 1d.4 off end # Intel PSE DMA1
172 device pci 1d.5 off end # Intel PSE DMA2
173 device pci 1d.6 off end # Intel PSE PWM
174 device pci 1d.7 off end # Intel PSE ADC
176 device pci 1e.0 off end # UART0
177 device pci 1e.1 off end # UART1
178 device pci 1e.2 off end # GSPI0
179 device pci 1e.3 off end # GSPI1
180 device pci 1e.4 off end # PCH Time-Sensitive Networking GbE
181 device pci 1e.6 off end # HPET
182 device pci 1e.7 off end # IOAPIC
184 device pci 1f.0 on # eSPI interface
185 chip superio/ite/it8613e
186 device pnp 2e.0 off end
187 device pnp 2e.1 on # COM 1
188 io 0x60 = 0x3f8
189 irq 0x70 = 4
191 device pnp 2e.4 off end # Environment Controller
192 device pnp 2e.5 off end # Keyboard
193 device pnp 2e.6 off end # Mouse
194 device pnp 2e.7 off end # GPIO
195 device pnp 2e.a off end # CIR
197 chip drivers/pc80/tpm
198 device pnp 0c31.0 on end
201 device pci 1f.1 on end # P2SB
202 device pci 1f.2 hidden end # Power Management Controller
203 device pci 1f.3 on end # Intel cAVS/HDA
204 device pci 1f.4 on end # SMBUS
205 device pci 1f.5 on end # PCH SPI (flash & TPM)
206 device pci 1f.7 off end # PCH Intel Trace Hub