src/mainboard/protectli/vault_kbl/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "1"
   7         register "deep_s5_enable_dc" = "1"
   8         register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
   9         register "s0ix_enable" = true
  10
  11         register "gpe0_dw0" = "GPP_B"
  12         register "gpe0_dw1" = "GPP_D"
  13         register "gpe0_dw2" = "GPP_E"
  14
  15         register "eist_enable" = "true"
  16
  17         # Disable DPTF
  18         register "dptf_enable" = "0"
  19
  20         register "tcc_offset" = "5" # TCC of 95C
  21
  22         # FSP Configuration
  23         register "DspEnable" = "0"
  24         register "IoBufferOwnership" = "0"
  25         register "SkipExtGfxScan" = "1"
  26         register "SaGv" = "SaGv_Enabled"
  27         register "IslVrCmd" = "2"
  28         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  29         register "PmConfigSlpS4MinAssert" = "4"         # 4s
  30         register "PmConfigSlpSusMinAssert" = "1"        # 500ms
  31         register "PmConfigSlpAMinAssert" = "3"          # 2s
  32
  33         # VR Settings Configuration for 4 Domains
  34         #+----------------+-------+-------+-------+-------+
  35         #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
  36         #+----------------+-------+-------+-------+-------+
  37         #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
  38         #| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
  39         #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
  40         #| Psi3Enable     | 1     | 1     | 1     | 1     |
  41         #| Psi4Enable     | 1     | 1     | 1     | 1     |
  42         #| ImonSlope      | 0     | 0     | 0     | 0     |
  43         #| ImonOffset     | 0     | 0     | 0     | 0     |
  44         #| IccMax         | 7A    | 34A   | 35A   | 35A   |
  45         #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
  46         #| AcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
  47         #| DcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
  48         #+----------------+-------+-------+-------+-------+
  49         #Note: IccMax settings are moved to SoC code
  50         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  51                 .vr_config_enable = 1,
  52                 .psi1threshold = VR_CFG_AMP(20),
  53                 .psi2threshold = VR_CFG_AMP(4),
  54                 .psi3threshold = VR_CFG_AMP(1),
  55                 .psi3enable = 1,
  56                 .psi4enable = 1,
  57                 .imon_slope = 0x0,
  58                 .imon_offset = 0x0,
  59                 .voltage_limit = 1520,
  60         }"
  61
  62         register "domain_vr_config[VR_IA_CORE]" = "{
  63                 .vr_config_enable = 1,
  64                 .psi1threshold = VR_CFG_AMP(20),
  65                 .psi2threshold = VR_CFG_AMP(5),
  66                 .psi3threshold = VR_CFG_AMP(1),
  67                 .psi3enable = 1,
  68                 .psi4enable = 1,
  69                 .imon_slope = 0x0,
  70                 .imon_offset = 0x0,
  71                 .voltage_limit = 1520,
  72         }"
  73
  74         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  75                 .vr_config_enable = 1,
  76                 .psi1threshold = VR_CFG_AMP(20),
  77                 .psi2threshold = VR_CFG_AMP(5),
  78                 .psi3threshold = VR_CFG_AMP(1),
  79                 .psi3enable = 1,
  80                 .psi4enable = 1,
  81                 .imon_slope = 0x0,
  82                 .imon_offset = 0x0,
  83                 .voltage_limit = 1520,
  84         }"
  85
  86         register "domain_vr_config[VR_GT_SLICED]" = "{
  87                 .vr_config_enable = 1,
  88                 .psi1threshold = VR_CFG_AMP(20),
  89                 .psi2threshold = VR_CFG_AMP(5),
  90                 .psi3threshold = VR_CFG_AMP(1),
  91                 .psi3enable = 1,
  92                 .psi4enable = 1,
  93                 .imon_slope = 0x0,
  94                 .imon_offset = 0x0,
  95                 .voltage_limit = 1520,
  96         }"
  97
  98         # Send an extra VR mailbox command for the PS4 exit issue
  99         register "SendVrMbxCmd" = "2"
 100
 101         register "SerialIoDevMode" = "{
 102                 [PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
 103                 [PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
 104                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 105                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 106                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 107                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 108                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
 109                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
 110                 [PchSerialIoIndexUart0] = PchSerialIoDisabled,
 111                 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
 112                 [PchSerialIoIndexUart2] = PchSerialIoDisabled,
 113         }"
 114
 115         device domain 0 on
 116                 device ref igpu         on  end
 117                 device ref south_xhci   on
 118                         register "usb2_ports" = "{
 119                                 [0]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 120                                 [1]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 121                                 [2]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 122                                 [3]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 123                                 [4]  = USB2_PORT_SHORT(OC_SKIP),        // Type-A Port
 124                                 [5]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 125                                 [6]  = USB2_PORT_SHORT(OC_SKIP),        // TYPE-A Port
 126                                 [7]  = USB2_PORT_SHORT(OC_SKIP),        // mPCIe slot
 127                         }"
 128
 129                         register "usb3_ports" = "{
 130                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       // TYPE-A Port
 131                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       // TYPE-A Port
 132                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       // TYPE-A Port
 133                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       // TYPE-A Port
 134                         }"
 135                 end
 136                 device ref heci1        on  end
 137                 device ref sata         on
 138                         register "SataPortsEnable" = "{
 139                                 [0] = 1,
 140                                 [1] = 1,
 141                         }"
 142                 end
 143                 device ref pcie_rp1     on
 144                         # LAN
 145                         register "PcieRpEnable[0]" = "1"
 146                         register "PcieRpAdvancedErrorReporting[0]" = "1"
 147                         register "PcieRpLtrEnable[0]" = "1"
 148                         register "PcieRpClkSrcNumber[0]" = "0"
 149                 end
 150                 device ref pcie_rp2     on
 151                         # LAN
 152                         register "PcieRpEnable[1]" = "1"
 153                         register "PcieRpAdvancedErrorReporting[1]" = "1"
 154                         register "PcieRpLtrEnable[1]" = "1"
 155                         register "PcieRpClkSrcNumber[1]" = "1"
 156                 end
 157                 device ref pcie_rp3     on
 158                         # LAN
 159                         register "PcieRpEnable[2]" = "1"
 160                         register "PcieRpAdvancedErrorReporting[2]" = "1"
 161                         register "PcieRpLtrEnable[2]" = "1"
 162                         register "PcieRpClkSrcNumber[2]" = "2"
 163                 end
 164                 device ref pcie_rp4     on
 165                         # LAN
 166                         register "PcieRpEnable[3]" = "1"
 167                         register "PcieRpAdvancedErrorReporting[3]" = "1"
 168                         register "PcieRpLtrEnable[3]" = "1"
 169                         register "PcieRpClkSrcNumber[3]" = "3"
 170                 end
 171                 device ref pcie_rp5     on
 172                         # LAN
 173                         register "PcieRpEnable[4]" = "1"
 174                         register "PcieRpAdvancedErrorReporting[4]" = "1"
 175                         register "PcieRpLtrEnable[4]" = "1"
 176                         register "PcieRpClkSrcNumber[4]" = "4"
 177                 end
 178                 device ref pcie_rp6     on
 179                         # LAN
 180                         register "PcieRpEnable[5]" = "1"
 181                         register "PcieRpAdvancedErrorReporting[5]" = "1"
 182                         register "PcieRpLtrEnable[5]" = "1"
 183                         register "PcieRpClkSrcNumber[5]" = "5"
 184                 end
 185                 device ref pcie_rp9     on
 186                         # mPCIe WIFI
 187                         register "PcieRpEnable[8]" = "1"
 188                         register "PcieRpAdvancedErrorReporting[8]" = "1"
 189                         register "PcieRpLtrEnable[8]" = "1"
 190                         register "PcieRpClkSrcNumber[8]" = "5"
 191                         register "PcieRpClkReqSupport[8]" = "1"
 192                         register "PcieRpClkReqNumber[8]" = "0"
 193                         smbios_slot_desc
 194                                 "SlotTypePciExpressMini52pinWithoutBSKO"
 195                                 "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
 196                 end
 197                 device ref lpc_espi     on
 198                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 199
 200                         register "gen1_dec" = "0x00fc0201"
 201                         register "gen2_dec" = "0x007c0a01"
 202                         register "gen3_dec" = "0x000c03e1"
 203                         register "gen4_dec" = "0x001c02e1"
 204                         chip superio/ite/it8772f
 205                                 register "TMPIN1.mode" = "THERMAL_RESISTOR"
 206                                 register "TMPIN2.mode" = "THERMAL_RESISTOR"
 207                                 register "TMPIN3.mode" = "THERMAL_PECI"
 208                                 # FAN2 available on fan header but unused
 209                                 device pnp 2e.0 off end # FDC
 210                                 device pnp 2e.1 on # Serial Port 1
 211                                         io 0x60 = 0x3f8
 212                                         irq 0x70 = 4
 213                                 end
 214                                 device pnp 2e.4 on # Environment Controller
 215                                         io 0x60 = 0xa40
 216                                         io 0x62 = 0xa30
 217                                         irq 0x70 = 9
 218                                 end
 219                                 device pnp 2e.5 off end # Keyboard
 220                                 device pnp 2e.6 off end # Mouse
 221                                 device pnp 2e.7 off end # GPIO
 222                                 device pnp 2e.a off end # IR
 223                         end
 224                 end
 225                 device ref smbus        on  end
 226         end
 227         chip drivers/crb
 228                 device mmio 0xfed40000 on end
 229         end
 230 end